Angel Pons submitted this change.
nb/intel/haswell: Configure VCs on Egress Port
System BIOS needs to program the Virtual Channel configuration.
Change-Id: Ic8ff17b3a1c4414633a658c60f2c4f7b195e5825
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43821
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/northbridge/intel/haswell/northbridge.c
1 file changed, 17 insertions(+), 0 deletions(-)
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 5c9ef74..99621c2 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -418,6 +418,22 @@
pci_write_config32(host_dev, DEVEN, deven);
}
+static void init_egress(void)
+{
+ /* VC0: Enable, ID0, TC0 */
+ EPBAR32(EPVC0RCTL) = (1 << 31) | (0 << 24) | (1 << 0);
+
+ /* No Low Priority Extended VCs, one Extended VC */
+ EPBAR32(EPPVCCAP1) = (0 << 4) | (1 << 0);
+
+ /* VC1: Enable, ID1, TC1 */
+ EPBAR32(EPVC1RCTL) = (1 << 31) | (1 << 24) | (1 << 1);
+
+ /* Poll the VC1 Negotiation Pending bit */
+ while ((EPBAR16(EPVC1RSTS) & (1 << 1)) != 0)
+ ;
+}
+
static void northbridge_dmi_init(void)
{
const bool is_haswell_h = !CONFIG(INTEL_LYNXPOINT_LP);
@@ -462,6 +478,7 @@
{
u8 bios_reset_cpl, pair;
+ init_egress();
northbridge_dmi_init();
/* Enable Power Aware Interrupt Routing. */
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