John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39479 )
Change subject: src/soc/tigerlake_dev: Update PMC IPC Hardware ID ......................................................................
src/soc/tigerlake_dev: Update PMC IPC Hardware ID
Change PMC IPC HID from INT34D2 to INTC1026 along with new kernel pmc ipc driver.
BUG=b:148949891 BRANCH=none TEST=Boot on Volteer and validate DP tunneling.
Change-Id: I987e7bf76ad1f8ff534101c80661f7c027a60b51 Signed-off-by: John Zhao john.zhao@intel.com --- A src/soc/intel/tigerlake/acpi/pmc.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 2 files changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39479/1
diff --git a/src/soc/intel/tigerlake/acpi/pmc.asl b/src/soc/intel/tigerlake/acpi/pmc.asl new file mode 100644 index 0000000..0d62edd --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pmc.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> + +Scope (_SB.PCI0) { + + Device (PMC) + { + Name (_HID, "INTC1026") + Name (_DDN, "Intel(R) Tiger Lake IPC Controller") + /* + * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF. + * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. + */ + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000) + }) + } +} diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 8593d07..9d25a73 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -40,6 +40,9 @@ /* PCIE Ports */ #include "pcie.asl"
+/* pmc 0:1f.2 */ +#include "pmc.asl" + /* Serial IO */ #include "serialio.asl"
Divya S Sasidharan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39479 )
Change subject: src/soc/tigerlake_dev: Update PMC IPC Hardware ID ......................................................................
Patch Set 1: Code-Review+1
Thanks John.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39479 )
Change subject: src/soc/tigerlake_dev: Update PMC IPC Hardware ID ......................................................................
Patch Set 1:
Add Topic information.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39479 )
Change subject: src/soc/tigerlake_dev: Update PMC IPC Hardware ID ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39479 )
Change subject: src/soc/tigerlake_dev: Update PMC IPC Hardware ID ......................................................................
src/soc/tigerlake_dev: Update PMC IPC Hardware ID
Change PMC IPC HID from INT34D2 to INTC1026 along with new kernel pmc ipc driver.
BUG=b:148949891 BRANCH=none TEST=Boot on Volteer and validate DP tunneling.
Change-Id: I987e7bf76ad1f8ff534101c80661f7c027a60b51 Signed-off-by: John Zhao john.zhao@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39479 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Divya S Sasidharan divya.s.sasidharan@intel.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com --- A src/soc/intel/tigerlake/acpi/pmc.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 2 files changed, 36 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Divya S Sasidharan: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/acpi/pmc.asl b/src/soc/intel/tigerlake/acpi/pmc.asl new file mode 100644 index 0000000..0d62edd --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pmc.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> + +Scope (_SB.PCI0) { + + Device (PMC) + { + Name (_HID, "INTC1026") + Name (_DDN, "Intel(R) Tiger Lake IPC Controller") + /* + * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF. + * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. + */ + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000) + }) + } +} diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 8593d07..9d25a73 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -40,6 +40,9 @@ /* PCIE Ports */ #include "pcie.asl"
+/* pmc 0:1f.2 */ +#include "pmc.asl" + /* Serial IO */ #include "serialio.asl"
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39479 )
Change subject: src/soc/tigerlake_dev: Update PMC IPC Hardware ID ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39479/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/pmc.asl:
https://review.coreboot.org/c/coreboot/+/39479/2/src/soc/intel/tigerlake/acp... PS2, Line 23: Tiger Lake Is this Tiger Lake specific device? I believe _HID INTC1026 refers to PMC IPC Controller for any Intel platform? If not right now, I think we should think if this should end up in common code like: https://review.coreboot.org/c/coreboot/+/39370
https://review.coreboot.org/c/coreboot/+/39479/2/src/soc/intel/tigerlake/acp... PS2, Line 29: 0x00010000 PCH_PWRM_BASE_SIZE
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Divya S Sasidharan (Code Review) -
Furquan Shaikh (Code Review)
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John Zhao (Code Review)
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Patrick Georgi (Code Review)
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Wonkyu Kim (Code Review)