[XS] Change in coreboot[main]: mb/google/ovis/var/deku: Set TCC_offset to 5

[Tony Huang (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun.

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82614?usp=email )

Change subject: mb/google/ovis/var/deku: Set TCC_offset to 5
......................................................................

mb/google/ovis/var/deku: Set TCC_offset to 5

Adjust settings as recommended by thermal team.

Set tcc_offset value to 5 in devicetree.

BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
     built bootleg and verified test result by thermal team

Change-Id: I30f54ae6017c54c91ff9b432bba0ebd5bfc65ab9
Signed-off-by: Tony Huang 
---
M src/mainboard/google/rex/variants/deku/overridetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/82614/1

diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb
index 5e3f250..8344e3b 100644
--- a/src/mainboard/google/rex/variants/deku/overridetree.cb
+++ b/src/mainboard/google/rex/variants/deku/overridetree.cb
@@ -27,6 +27,9 @@
    	[DDI_PORT_4] = DDI_ENABLE_HPD,
    }"

+	# Temporary setting TCC of 105C = Tj max (110) - TCC_Offset (5)
+	register "tcc_offset" = "5"
+
    register "serial_io_i2c_mode" = "{
    	[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
    	[PchSerialIoIndexI2C1] = PchSerialIoDisabled,