Attention is currently required from: Sridhar Siricilla, Nick Vaccaro, Balaji Manigandan, Krishna P Bhat D, Karthik Ramasubramanian. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58679 )
Change subject: util/spd_tools: Add LP5 support for ADL ......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8: It’s been bothering me how ADL-specific this implementation is. E.g. not including tCKmax or the CAS latencies as attributes since the ADL MRC doesn’t use them, assuming 4:1 WCK:CK and 8B bank mode only, etc.
My reasoning is that it’s not worth trying to generalise the code at this stage since I have no idea what the commonalities and differences between platforms will be. This is partly because there’s no LP5 SPD spec, so there’s a lot of room for SoC vendors to make their own decisions. I would assume future Intel platforms will be relatively similar to ADL, but if we have any AMD platforms using LP5 they could do something very different. So my plan is to just wait and see what other platforms do, and generalise the code as needed then.
If anyone has thoughts on this, let me know.
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Reka Norman (Code Review)