Attention is currently required from: Rizwan Qureshi, Meera Ravindranath. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59392 )
Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2 ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59392/comment/c1356599_c91e51c0 PS2, Line 9: commit:3fd39467b Fix S0ix regression
Clksrc 3 disable is needed for S0ix regression. […]
Note: if you disable the CLKSRC from strap as well, then also you are doing things statically which is similar to disable in coreboot. You need solution that is dynamic. Do you want to compromise on the capability to have device connected to CPU PCIe ?
I guess we wish to manage dynamic clock gating based on implementing IPC to PMC. Myself and Tim are working towards the implementation for CPU PCIe as here b:197983574
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Subrata Banik (Code Review)