Change in ...coreboot[master]: UPSTREAM: mb/google/octopus: Override emmc DLL values for Meep
Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31021
Change subject: UPSTREAM: mb/google/octopus: Override emmc DLL values for Meep ......................................................................
UPSTREAM: mb/google/octopus: Override emmc DLL values for Meep
New emmc DLL values for Meep.
BUG=b:120561055 TEST=Boot to OS on 13 systems
Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad Signed-off-by: Kane Chen kane.chen@intel.com --- M src/mainboard/google/octopus/variants/meep/overridetree.cb 1 file changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31021/1
diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index f7aeac1..c639b73 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -1,5 +1,46 @@ chip soc/intel/apollolake
+ # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0b0d" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c2a2a2a" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00171a1a" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0b0b" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value |
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31021
to look at the new patch set (#2).
Change subject: UPSTREAM: mb/google/octopus: Override emmc DLL values for Meep ......................................................................
UPSTREAM: mb/google/octopus: Override emmc DLL values for Meep
New emmc DLL values for Meep.
BUG=b:122308271 TEST=Boot to OS on 13 Meep system
Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad Signed-off-by: Kane Chen kane.chen@intel.com --- M src/mainboard/google/octopus/variants/meep/overridetree.cb 1 file changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31021/2
Justin TerAvest has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31021 )
Change subject: UPSTREAM: mb/google/octopus: Override emmc DLL values for Meep ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31021 )
Change subject: UPSTREAM: mb/google/octopus: Override emmc DLL values for Meep ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31021/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31021/2//COMMIT_MSG@7 PS2, Line 7: UPSTREAM: Please remove this tag. It is used only in chromium gerrit.
Hello Justin TerAvest, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31021
to look at the new patch set (#3).
Change subject: mb/google/octopus: Override emmc DLL values for Meep ......................................................................
mb/google/octopus: Override emmc DLL values for Meep
New emmc DLL values for Meep.
BUG=b:122308271 TEST=Boot to OS on 13 Meep system
Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad Signed-off-by: Kane Chen kane.chen@intel.com --- M src/mainboard/google/octopus/variants/meep/overridetree.cb 1 file changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31021/3
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31021 )
Change subject: mb/google/octopus: Override emmc DLL values for Meep ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/31021/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31021/2//COMMIT_MSG@7 PS2, Line 7: UPSTREAM:
Please remove this tag. It is used only in chromium gerrit.
done, thanks for reminding
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31021 )
Change subject: mb/google/octopus: Override emmc DLL values for Meep ......................................................................
Patch Set 3: Code-Review+2
Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31021 )
Change subject: mb/google/octopus: Override emmc DLL values for Meep ......................................................................
mb/google/octopus: Override emmc DLL values for Meep
New emmc DLL values for Meep.
BUG=b:122308271 TEST=Boot to OS on 13 Meep system
Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad Signed-off-by: Kane Chen kane.chen@intel.com Reviewed-on: https://review.coreboot.org/c/31021 Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Justin TerAvest teravest@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/octopus/variants/meep/overridetree.cb 1 file changed, 41 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Justin TerAvest: Looks good to me, approved
diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index f7aeac1..c639b73 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -1,5 +1,46 @@ chip soc/intel/apollolake
+ # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0b0d" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c2a2a2a" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00171a1a" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0b0b" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value |
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Furquan Shaikh (Code Review) -
Justin TerAvest (Code Review)
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Kane Chen (Code Review)