Change in ...coreboot[master]: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29908

Change subject: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage
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[TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage

Change-Id: Ic31702514cf84e3480b622c28cd2857e613869d9
Signed-off-by: Arthur Heymans 
---
M src/drivers/intel/fsp1_0/Makefile.inc
M src/soc/intel/fsp_broadwell_de/Kconfig
M src/soc/intel/fsp_broadwell_de/Makefile.inc
A src/soc/intel/fsp_broadwell_de/exit_car_fsp.S
4 files changed, 44 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/29908/1

diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 67741a9..b75afad 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -17,6 +17,7 @@

ramstage-y += fsp_util.c hob.c
 romstage-y += fsp_util.c hob.c
+postcar-y += fsp_util.c hob.c

ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
 romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig
index fe0fa8d..1203555 100644
--- a/src/soc/intel/fsp_broadwell_de/Kconfig
+++ b/src/soc/intel/fsp_broadwell_de/Kconfig
@@ -28,6 +28,8 @@
    select HAVE_SMI_HANDLER
    select TSC_MONOTONIC_TIMER
    select TSC_CONSTANT_RATE
+	select POSTCAR_STAGE
+	select POSTCAR_CONSOLE

config VBOOT
    select VBOOT_STARTS_IN_ROMSTAGE
diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc
index f88cbba..36d907a 100644
--- a/src/soc/intel/fsp_broadwell_de/Makefile.inc
+++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc
@@ -19,6 +19,7 @@
 ramstage-y += tsc_freq.c
 romstage-y += memmap.c
 ramstage-y += memmap.c
+postcar-y += memmap.c
 ramstage-y += southcluster.c
 ramstage-y += acpi.c
 ramstage-y += smbus_common.c
@@ -38,4 +39,6 @@
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/

+postcar-y += exit_car_fsp.S
+
 endif # ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y)
diff --git a/src/soc/intel/fsp_broadwell_de/exit_car_fsp.S b/src/soc/intel/fsp_broadwell_de/exit_car_fsp.S
new file mode 100644
index 0000000..4ac580c
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/exit_car_fsp.S
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cr.h>
+
+/*
+ * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.
+ * This version of chipset_teardown_car sets up the stack, then bypasses
+ * the rest of arch/x86/exit_car.S and calls main() itself instead of
+ * returning to _start. In main(), the TempRamExit FSP API is called
+ * to tear down the CAR and set up caching which can be overwritten
+ * after the API call.  More info can be found in the FSP Integration
+ * Guide included with the FSP binary.
+ */
+
+.text
+.global chipset_teardown_car
+chipset_teardown_car:
+
+	/* Set up new stack. */
+	mov	post_car_stack_top, %esp
+
+	/* Call C code */
+	call	main