[S] Change in coreboot[master]: [NEEDSTEST]soc/intel/alderlake: Disable PCIe clock gating

[Patrick Rudolph (Code Review)]

Attention is currently required from: Angel Pons, Subrata Banik, Tarun Tuli.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76687?usp=email )

Change subject: [NEEDSTEST]soc/intel/alderlake: Disable PCIe clock gating
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Patch Set 1:

(1 comment)

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/76687/comment/452b79ff_476f0172 :
PS1, Line 923: #if CONFIG(FSP_TYPE_IOT)
> What is this guard for? Does Client FSP not have these UPDs?

It has the same UPDs, but it haven't been updated yet, thus the UPD is still missing.