Change in coreboot[master]: cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_SIPI

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56651 )

Change subject: cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_SIPI
......................................................................

cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_SIPI

This patch renames X86_AMD_INIT_SIPI Kconfig to leverage this logic
on latest Intel platform.

Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62
Signed-off-by: Subrata Banik 
---
M src/cpu/x86/Kconfig
M src/cpu/x86/mp_init.c
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/picasso/Kconfig
4 files changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/56651/1

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index a5c2a4d..9991f7a 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -167,14 +167,14 @@
      This option informs the MTRR code to use the RdMem and WrMem fields
      in the fixed MTRR MSRs.

-config X86_AMD_INIT_SIPI
+config X86_INIT_SIPI
    bool
    default n
    help
      This option limits the number of SIPI signals sent during during the
      common AP setup.  Intel documentation specifies an INIT SIPI SIPI
      sequence, however this doesn't work on some AMD platforms. These
-	  newer AMD platforms don't need the 10ms wait between INIT and SIPI,
+	  newer AMD, Intel platforms don't need the 10ms wait between INIT and SIPI,
      so skip that too to save some time.

config SOC_SETS_MSRS
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 3eef355..8640f7e 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -450,7 +450,7 @@
    /* Send INIT IPI to all but self. */
    lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT, 0);

-	if (!CONFIG(X86_AMD_INIT_SIPI)) {
+	if (!CONFIG(X86_INIT_SIPI)) {
    	printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n");
    	mdelay(10);
    }
@@ -477,7 +477,7 @@
    /* Wait for CPUs to check in up to 200 us. */
    wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */);

-	if (CONFIG(X86_AMD_INIT_SIPI))
+	if (CONFIG(X86_INIT_SIPI))
    	return 0;

/* Send 2nd SIPI */
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index fab31d4..27a5c14 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -74,7 +74,7 @@
    select TIMER_QUEUE
    select UDK_2017_BINDING
    select X86_AMD_FIXED_MTRRS
-	select X86_AMD_INIT_SIPI
+	select X86_INIT_SIPI

config ARCH_ALL_STAGES_X86
    default n
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index eb1780a..61d45b8 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -16,7 +16,7 @@
    select ARCH_X86
    select RESET_VECTOR_IN_RAM
    select X86_AMD_FIXED_MTRRS
-	select X86_AMD_INIT_SIPI
+	select X86_INIT_SIPI
    select ACPI_SOC_NVS
    select DRIVERS_I2C_DESIGNWARE
    select DRIVERS_USB_PCI_XHCI