Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Cascade Lake SP support ......................................................................
soc/intel: Add Cascade Lake SP support
Adds Xeon Cascade Lake processor CPUIDs and Sky Lake-E DMI3 Host Bridge PCI Id
Change-Id: If351d554db62c51849ff6c7bb49074e587f14e6d Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/skylake/bootblock/report_platform.c 5 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35126/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ac70d8c..2727a6f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3176,6 +3176,7 @@ #define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f #define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 #define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f +#define PCI_DEVICE_ID_INTEL_SKL_ID_E 0x2020 #define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904 #define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c #define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index e0cee17..6a6ae17 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -56,11 +56,15 @@ { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0 }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0 }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HR0 }, + { X86_VENDOR_INTEL, CPUID_SKYLAKE_HMU0 }, { X86_VENDOR_INTEL, CPUID_KABYLAKE_G0 }, { X86_VENDOR_INTEL, CPUID_KABYLAKE_H0 }, { X86_VENDOR_INTEL, CPUID_KABYLAKE_Y0 }, { X86_VENDOR_INTEL, CPUID_KABYLAKE_HA0 }, { X86_VENDOR_INTEL, CPUID_KABYLAKE_HB0 }, + { X86_VENDOR_INTEL, CPUID_CASCADELAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_CASCADELAKE_BLR0 }, + { X86_VENDOR_INTEL, CPUID_CASCADELAKE_BLR1 }, { X86_VENDOR_INTEL, CPUID_CANNONLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_CANNONLAKE_B0 }, { X86_VENDOR_INTEL, CPUID_CANNONLAKE_C0 }, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 5ef7641..cf04659 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -21,6 +21,10 @@ /* Supported CPUIDs for different SOCs */ #define CPUID_SKYLAKE_C0 0x406e2 #define CPUID_SKYLAKE_D0 0x406e3 +#define CPUID_SKYLAKE_HMU0 0x50654 +#define CPUID_CASCADELAKE_A0 0x50655 +#define CPUID_CASCADELAKE_BLR0 0x50656 +#define CPUID_CASCADELAKE_BLR1 0x50657 #define CPUID_SKYLAKE_HQ0 0x506e1 #define CPUID_SKYLAKE_HR0 0x506e3 #define CPUID_KABYLAKE_G0 0x406e8 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index b7964e6..30ff7c9 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -349,6 +349,7 @@ PCI_DEVICE_ID_INTEL_KBL_ID_S, PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, PCI_DEVICE_ID_INTEL_SKL_ID_DT, + PCI_DEVICE_ID_INTEL_SKL_ID_E, PCI_DEVICE_ID_INTEL_KBL_ID_U, PCI_DEVICE_ID_INTEL_KBL_ID_Y, PCI_DEVICE_ID_INTEL_KBL_ID_H, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 279273f..f717678 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -41,6 +41,10 @@ { CPUID_KABYLAKE_Y0, "Kabylake Y0" }, { CPUID_KABYLAKE_HA0, "Kabylake H A0" }, { CPUID_KABYLAKE_HB0, "Kabylake H B0" }, + { CPUID_SKYLAKE_HMU0, "Skylake H0/M0/U0" }, + { CPUID_CASCADELAKE_A0, "Cascade Lake A0" }, + { CPUID_CASCADELAKE_BLR0, "Cascade Lake B0/L0/R0" }, + { CPUID_CASCADELAKE_BLR1, "Cascade Lake B1/L1/R1" }, };
static struct { @@ -56,6 +60,7 @@ { PCI_DEVICE_ID_INTEL_SKL_ID_H_2, "Skylake-H (2 Core)" }, { PCI_DEVICE_ID_INTEL_SKL_ID_S_2, "Skylake-S (2 Core)" }, { PCI_DEVICE_ID_INTEL_SKL_ID_S_4, "Skylake-S (4 Core)" }, + { PCI_DEVICE_ID_INTEL_SKL_ID_E, "Sky Lake-E" }, { PCI_DEVICE_ID_INTEL_KBL_ID_U, "Kabylake-U" }, { PCI_DEVICE_ID_INTEL_KBL_U_R, "Kabylake-R ULT"}, { PCI_DEVICE_ID_INTEL_KBL_ID_Y, "Kabylake-Y" },
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Cascade Lake SP support ......................................................................
Patch Set 3:
I might be splitting hairs here, but I don't think Cascade Lake SP is exactly a SoC... I guess this is better than duplicating lots of code though.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Cascade Lake SP support ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/35126/3/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/35126/3/src/soc/intel/skylake/bootb... PS3, Line 63: Sky Lake-E I would remove the space, so as to align with the other names:
Skylake-E
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35126
to look at the new patch set (#4).
Change subject: soc/intel: Add Cascade Lake SP support ......................................................................
soc/intel: Add Cascade Lake SP support
Adds Xeon Cascade Lake processor CPUIDs and SkyLake-E Host Bridge PCI Id
Change-Id: If351d554db62c51849ff6c7bb49074e587f14e6d Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/skylake/bootblock/report_platform.c 5 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35126/4
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Cascade Lake SP support ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35126/3/src/soc/intel/skylake/bootb... File src/soc/intel/skylake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/35126/3/src/soc/intel/skylake/bootb... PS3, Line 63: Sky Lake-E
I would remove the space, so as to align with the other names: […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Cascade Lake SP support ......................................................................
Patch Set 5: Code-Review+2
LGTM
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Cascade Lake SP support ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35126/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35126/6//COMMIT_MSG@10 PS6, Line 10: PCI Id Add . at the end of sentence.
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35126
to look at the new patch set (#7).
Change subject: soc/intel: Add Skylake-SP and Cascade Lake support ......................................................................
soc/intel: Add Skylake-SP and Cascade Lake support
Adds Xeon Skylake-SP and Cascade Lake processor CPUIDs and SkyLake-E Host Bridge PCI Id.
Change-Id: If351d554db62c51849ff6c7bb49074e587f14e6d Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/skylake/bootblock/report_platform.c 5 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35126/7
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Skylake-SP and Cascade Lake support ......................................................................
Patch Set 7: Code-Review+2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Skylake-SP and Cascade Lake support ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35126/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35126/7//COMMIT_MSG@7 PS7, Line 7: Add Skylake-SP as also I added cpuid for skylake-sp
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Skylake-SP and Cascade Lake support ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35126/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35126/7//COMMIT_MSG@7 PS7, Line 7: Add Skylake-SP
as also I added cpuid for skylake-sp
But how you tested? So far there's no coreboot platform published to support skylake-sp server yet.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Skylake-SP and Cascade Lake support ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35126/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35126/6//COMMIT_MSG@10 PS6, Line 10: PCI Id
Add . at the end of sentence.
Done
https://review.coreboot.org/c/coreboot/+/35126/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35126/7//COMMIT_MSG@7 PS7, Line 7: Add Skylake-SP
But how you tested? So far there's no coreboot platform published to support skylake-sp server yet.
Not tested yet. We are waiting for Intel to answer the question about fsp for these processors
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Skylake-SP and Cascade Lake support ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35126/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35126/7//COMMIT_MSG@7 PS7, Line 7: Add Skylake-SP
Not tested yet. […]
I think the Supermicro board you mentioned on other changes has BootGuard enabled, not sure about the Intel server board though...
With BootGuard enabled, running coreboot becomes pretty much impossible unless you have the signing keys. I would suggest checking if your boards have BootGuard enabled or not, so that the effort isn't in vain.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Skylake-SP and Cascade Lake support ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35126/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35126/7//COMMIT_MSG@7 PS7, Line 7: Add Skylake-SP
I think the Supermicro board you mentioned on other changes has BootGuard enabled, not sure about th […]
IMO, no matter what Intel does about FSP, integrating Skylake SP support should come after a huge restructuring of the whole soc/intel/ code. With such a platform, having the code in soc/ makes even less sense that it makes for the smaller PCH-H platforms now.
Please don't waste time with half-baked patches before there is a bigger plan to integrate this platform. The only thing we can achive atm, is even more congestion in this area.
Maxim Polyakov has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35126 )
Change subject: soc/intel: Add Skylake-SP and Cascade Lake support ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Lance Zhao (Code Review)
-
Maxim Polyakov (Code Review)
-
Nico Huber (Code Review)