Maxim Polyakov uploaded patch set #7 to this change.

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soc/intel: Add Skylake-SP and Cascade Lake support

Adds Xeon Skylake-SP and Cascade Lake processor CPUIDs and SkyLake-E
Host Bridge PCI Id.

Change-Id: If351d554db62c51849ff6c7bb49074e587f14e6d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/skylake/bootblock/report_platform.c
5 files changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35126/7

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If351d554db62c51849ff6c7bb49074e587f14e6d
Gerrit-Change-Number: 35126
Gerrit-PatchSet: 7
Gerrit-Owner: Maxim Polyakov <max.senia.poliak@gmail.com>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak@gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Lance Zhao <lance.zhao@gmail.com>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: newpatchset