Change in coreboot[master]: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi
This patch creates a common instance of lpc.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask specific soc code to refer lpc.asl from common code block.
Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI rather LPC.
TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify Device(LPCB) device presence after booting to OS.
Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87 Signed-off-by: Subrata Banik subrata.banik@intel.com --- D src/soc/intel/apollolake/acpi/lpc.asl M src/soc/intel/apollolake/acpi/southbridge.asl M src/soc/intel/cannonlake/acpi/southbridge.asl R src/soc/intel/common/block/acpi/acpi/lpc.asl M src/soc/intel/denverton_ns/acpi/lpc.asl M src/soc/intel/denverton_ns/include/soc/iomap.h D src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/skylake/acpi/lpc.asl 9 files changed, 48 insertions(+), 340 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/36455/1
diff --git a/src/soc/intel/apollolake/acpi/lpc.asl b/src/soc/intel/apollolake/acpi/lpc.asl deleted file mode 100644 index 749daf7..0000000 --- a/src/soc/intel/apollolake/acpi/lpc.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel LPC Bus Device - 0:1f.0 */ - -Device (LPCB) -{ - Name (_ADR, 0x001f0000) -} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 7c9c873..9acb9ae 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -33,7 +33,7 @@ #include "xhci.asl"
/* LPC */ -#include "lpc.asl" +#include <soc/intel/common/block/acpi/acpi/lpc.asl>
/* eMMC */ #include "scs.asl" diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 8ba3d89..b52de65 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -32,7 +32,7 @@ #endif
/* LPC 0:1f.0 */ -#include "lpc.asl" +#include <soc/intel/common/block/acpi/acpi/lpc.asl>
/* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/cannonlake/acpi/lpc.asl b/src/soc/intel/common/block/acpi/acpi/lpc.asl similarity index 78% rename from src/soc/intel/cannonlake/acpi/lpc.asl rename to src/soc/intel/common/block/acpi/acpi/lpc.asl index f1c1bf3..b0f981c 100644 --- a/src/soc/intel/cannonlake/acpi/lpc.asl +++ b/src/soc/intel/common/block/acpi/acpi/lpc.asl @@ -1,9 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,11 +13,28 @@ * GNU General Public License for more details. */
+/* Intel LPC/eSPI Bus Device - 0:1f.0 */ + Device (LPCB) { Name (_ADR, 0x001f0000) Name (_DDN, "LPC Bus Device")
+ /* DMA Controller */ + Device (DMAC) + { + Name (_HID, EISAID("PNP0200")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } + }) + } + + /* Firmware Hub */ Device (FWH) { Name (_HID, EISAID ("INT0800")) @@ -30,9 +45,11 @@ }) }
+ /* High Precision Event Timer */ Device (HPET) { Name (_HID, EISAID ("PNP0103")) + Name (_CID, 0x010CD041) Name (_DDN, "High Precision Event Timer") Name (_CRS, ResourceTemplate () { @@ -40,10 +57,22 @@ }) Method (_STA, 0) { - Return (0xf) + Return (0xF) } }
+ /* FPU */ + Device(MATH) + { + Name (_HID, EISAID("PNP0C04")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) + IRQNoFlags() { 13 } + }) + } + + /* AT Interrupt Controller */ Device (PIC) { Name (_HID, EISAID ("PNP0000")) @@ -71,6 +100,7 @@ }) }
+ /* LPC device: Resource consumption */ Device (LDRC) { Name (_HID, EISAID ("PNP0C02")) @@ -92,6 +122,7 @@ }) }
+ /* Real Time Clock Device */ Device (RTC) { Name (_HID, EISAID ("PNP0B00")) @@ -102,6 +133,7 @@ }) }
+ /* Timer */ Device (TIMR) { Name (_HID, EISAID ("PNP0100")) @@ -113,5 +145,4 @@ IRQNoFlags () {0} }) } - } diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl index cc36451..4b6e786 100644 --- a/src/soc/intel/denverton_ns/acpi/lpc.asl +++ b/src/soc/intel/denverton_ns/acpi/lpc.asl @@ -16,10 +16,11 @@ */
// Intel LPC Bus Device - 0:1f.0 +#include <soc/intel/common/block/acpi/acpi/lpc.asl>
-Device (LPCB) +Scope (_SB.PCI0.LPCB) { - Name(_ADR, 0x001f0000) + #include "irqlinks.asl"
OperationRegion(LPC0, PCI_Config, 0x00, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) @@ -29,8 +30,6 @@ IOD1, 8, }
- #include "irqlinks.asl" - Device(APIC) // IO APIC { Name(_HID,EISAID("PNP0003")) @@ -40,96 +39,6 @@ }) }
- Device (HPET) - { - Name (_HID, EISAID("PNP0103")) - Name (_CID, 0x010CD041) - - Method (_STA, 0) // Device Status - { - Return (0xF) // Enable and show device - } - - Name(_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, DEFAULT_HPET_ADDR, 0x400) - }) - } - - Device(PIC) // 8259 Interrupt Controller - { - Name(_HID,EISAID("PNP0000")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 2) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x70, 0x70, 0x1, 0x01) // NMI Enable. - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap - - // BIOS ROM shadow memory range - Memory32Fixed(ReadOnly, 0x000E0000, 0x20000) - - // BIOS flash 16MB - Memory32Fixed(ReadOnly,0xFF000000,0x1000000) - }) - } - - Device (RTC) // Real Time Clock - { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } - }) - } - - Device (TIMR) // Intel 8254 timer - { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} - }) - } - Device(IUR3) // Internal UART 1 { Name(_HID, EISAID("PNP0501")) diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index 8bcef91..c512d55 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -31,6 +31,8 @@ #define ACPI_BASE_ADDRESS DEFAULT_PMBASE #define DEFAULT_TCO_BASE 0x400
+#define HPET_BASE_ADDRESS 0xfed00000 + /* Southbridge internal device MEM BARs (Set to match FSP settings) */ #define DEFAULT_PCR_BASE 0xfd000000 #define DEFAULT_PWRM_BASE 0xfe000000 diff --git a/src/soc/intel/icelake/acpi/espi.asl b/src/soc/intel/icelake/acpi/espi.asl deleted file mode 100644 index 4456812..0000000 --- a/src/soc/intel/icelake/acpi/espi.asl +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/* Device identifier is not changed to ESPI to maintain coherency with ec.asl */ -Device (LPCB) -{ - Name (_ADR, 0x001f0000) - Name (_DDN, "ESPI Bus Device") - - Device (FWH) - { - Name (_HID, EISAID ("INT0800")) - Name (_DDN, "Firmware Hub") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID ("PNP0103")) - Name (_DDN, "High Precision Event Timer") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - Method (_STA, 0) - { - Return (0xf) - } - } - - Device (PIC) - { - Name (_HID, EISAID ("PNP0000")) - Name (_DDN, "8259 Interrupt Controller") - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device (LDRC) - { - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 2) - Name (_DDN, "Legacy Device Resources") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, - 0x1, 0xff) - }) - } - - Device (RTC) - { - Name (_HID, EISAID ("PNP0B00")) - Name (_DDN, "Real Time Clock") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x70, 0x70, 1, 8) - }) - } - - Device (TIMR) - { - Name (_HID, EISAID ("PNP0100")) - Name (_DDN, "8254 Timer") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags () {0} - }) - } - -} diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index ffd2fcc..389963e 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -33,7 +33,7 @@ #include "gpio.asl"
/* ESPI 0:1f.0 */ -#include "espi.asl" +#include <soc/intel/common/block/acpi/acpi/lpc.asl>
/* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl index c9167ad..7dd0298 100644 --- a/src/soc/intel/skylake/acpi/lpc.asl +++ b/src/soc/intel/skylake/acpi/lpc.asl @@ -15,105 +15,11 @@ * GNU General Public License for more details. */
-Device (LPCB) +// Intel LPC Bus Device - 0:1f.0 +#include <soc/intel/common/block/acpi/acpi/lpc.asl> + +Scope (_SB.PCI0.LPCB) { - Name (_ADR, 0x001f0000) - Name (_DDN, "LPC Bus Device") - - Device (FWH) - { - Name (_HID, EISAID ("INT0800")) - Name (_DDN, "Firmware Hub") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID ("PNP0103")) - Name (_DDN, "High Precision Event Timer") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - Method (_STA, 0) - { - Return (0xf) - } - } - - Device (PIC) - { - Name (_HID, EISAID ("PNP0000")) - Name (_DDN, "8259 Interrupt Controller") - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device (LDRC) - { - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 2) - Name (_DDN, "Legacy Device Resources") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, - 0x1, 0xff) - }) - } - - Device (RTC) - { - Name (_HID, EISAID ("PNP0B00")) - Name (_DDN, "Real Time Clock") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x70, 0x70, 1, 8) - }) - } - - Device (TIMR) - { - Name (_HID, EISAID ("PNP0100")) - Name (_DDN, "8254 Timer") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags () {0} - }) - } - #include <acpi/ec.asl> #include <acpi/superio.asl> }
Hello Raj Astekar, Aaron Durbin, Patrick Rudolph, Vanny E, Arthur Heymans, Aamir Bohra, Ravishankar Sarawadi, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36455
to look at the new patch set (#2).
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi
This patch creates a common instance of lpc.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask specific soc code to refer lpc.asl from common code block.
Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI rather LPC.
TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify Device(LPCB) device presence after booting to OS.
Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87 Signed-off-by: Subrata Banik subrata.banik@intel.com --- D src/soc/intel/apollolake/acpi/lpc.asl M src/soc/intel/apollolake/acpi/southbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/cannonlake/acpi/southbridge.asl R src/soc/intel/common/block/acpi/acpi/lpc.asl M src/soc/intel/denverton_ns/acpi/lpc.asl M src/soc/intel/denverton_ns/include/soc/iomap.h D src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/skylake/acpi/lpc.asl 10 files changed, 51 insertions(+), 340 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/36455/2
David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 2: Code-Review+1
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Nice cleanup!
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... PS2, Line 25: Device (DMAC) This one was not present on some devices. Do you expect this to be an issue?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... PS2, Line 25: Device (DMAC)
This one was not present on some devices. […]
i have started cycling test on all platform been touched here, so far no issue has seen. will post result after completing the test?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... PS2, Line 25: Device (DMAC)
i have started cycling test on all platform been touched here, so far no issue has seen. will post result after completing the test?
Nice.
Unrelated to this patch: could you give us some insight on how Intel tests their platforms? Some in the community are working to hook up some automatic QA testing on hardware to gerrit/jenkins and could likely benefit from that information.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... PS2, Line 25: Device (DMAC)
i have started cycling test on all platform been touched here, so far no issue has seen. […]
Nice idea to have some boot BOT like of logic to ensure all CL's are getting tested.
For our common code activity we do have test rack with all possible soc 1 unit to test common CL across. if not common code then ppl do use their own unit to verify CL before pushing. But its tough to maintain common code test rack with daily code sync ensures everything works fine, i hope you could able to imagine the situation :)
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... PS2, Line 25: Device (DMAC)
Nice idea to have some boot BOT like of logic to ensure all CL's are getting tested.
For our common code activity we do have test rack with all possible soc 1 unit to test common CL across. if not common code then ppl do use their own unit to verify CL before pushing. But its tough to maintain common code test rack with daily code sync ensures everything works fine, i hope you could able to imagine the situation :)
It is indeed quite challenging. The idea was to eventually be able to do limited hardware (basic things like testing if it boots to the OS, ACPI resume working, ...) testing on *every* CL in gerrit. That does impose some serious speed requirements on flashing and testing.
Some automatic regression / bisection could also be implemented and posted to the mailing list.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... PS2, Line 25: Device (DMAC)
Nice idea to have some boot BOT like of logic to ensure all CL's are getting tested. […]
indeed good idea, we (from intel) do see the need of doing such CL based automatic basic sanity check also i understood google also thinking to setup something.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 3: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/3/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/3/src/soc/intel/common/block/... PS3, Line 4: * Copyright (C) 2007-2009 coresystems GmbH IANAL but I don't think it is legit to remove these
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/3/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/3/src/soc/intel/common/block/... PS3, Line 4: * Copyright (C) 2007-2009 coresystems GmbH
IANAL but I don't think it is legit to remove these
With the move to AUTHORS file I think this can simply be dropped. I think that when a legal issue about copyright appears 'git blame' is what matters and not so much what authors feature at the top of files, IANAL either.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Nice clean-up.
https://review.coreboot.org/c/coreboot/+/36455/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36455/3//COMMIT_MSG@10 PS3, Line 10: ask asks
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36455/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36455/3//COMMIT_MSG@14 PS3, Line 14: rather rather than
https://review.coreboot.org/c/coreboot/+/36455/3/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/3/src/soc/intel/common/block/... PS3, Line 4: * Copyright (C) 2007-2009 coresystems GmbH
IANAL but I don't think it is legit to remove these […]
I'd leave the previous copyright lines because AUTHORS is not complete yet. Also, given the rather high similarity index, I would say dropping copyright lines is not a good idea.
IANAL either, so I would play safe: how about keeping the previous copyright years, and updating the years for Intel Corporation?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/3/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/3/src/soc/intel/common/block/... PS3, Line 4: * Copyright (C) 2007-2009 coresystems GmbH
I'd leave the previous copyright lines because AUTHORS is not complete yet. […]
Done
Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Michael Niewöhner, Aamir Bohra, Ravishankar Sarawadi, Paul Menzel, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, Raj Astekar, David Guckian, Vanny E, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36455
to look at the new patch set (#4).
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi
This patch creates a common instance of lpc.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask specific soc code to refer lpc.asl from common code block.
Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI rather LPC.
TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify Device(LPCB) device presence after booting to OS.
Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87 Signed-off-by: Subrata Banik subrata.banik@intel.com --- D src/soc/intel/apollolake/acpi/lpc.asl M src/soc/intel/apollolake/acpi/southbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/cannonlake/acpi/southbridge.asl R src/soc/intel/common/block/acpi/acpi/lpc.asl M src/soc/intel/denverton_ns/acpi/lpc.asl M src/soc/intel/denverton_ns/include/soc/iomap.h D src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/skylake/acpi/lpc.asl 10 files changed, 50 insertions(+), 337 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/36455/4
Hello Aaron Durbin, Patrick Rudolph, Arthur Heymans, Michael Niewöhner, Aamir Bohra, Ravishankar Sarawadi, Paul Menzel, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, Raj Astekar, David Guckian, Vanny E, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36455
to look at the new patch set (#5).
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi
This patch creates a common instance of lpc.asl inside intel common code (soc/intel/common/block/acpi/acpi) and asks specific soc code to refer lpc.asl from common code block.
Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI rather than LPC.
TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify Device(LPCB) device presence after booting to OS.
Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87 Signed-off-by: Subrata Banik subrata.banik@intel.com --- D src/soc/intel/apollolake/acpi/lpc.asl M src/soc/intel/apollolake/acpi/southbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/cannonlake/acpi/southbridge.asl R src/soc/intel/common/block/acpi/acpi/lpc.asl M src/soc/intel/denverton_ns/acpi/lpc.asl M src/soc/intel/denverton_ns/include/soc/iomap.h D src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/skylake/acpi/lpc.asl 10 files changed, 50 insertions(+), 337 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/36455/5
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36455/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36455/3//COMMIT_MSG@10 PS3, Line 10: ask
asks
Done
https://review.coreboot.org/c/coreboot/+/36455/3//COMMIT_MSG@14 PS3, Line 14: rather
rather than
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/3/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/3/src/soc/intel/common/block/... PS3, Line 4: * Copyright (C) 2007-2009 coresystems GmbH
Done
Sorry for opening that again. Not done. When you keep and update the Intel entry, then keep the others.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 6: Code-Review+1
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/3/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/3/src/soc/intel/common/block/... PS3, Line 4: * Copyright (C) 2007-2009 coresystems GmbH
Sorry for opening that again. Not done. […]
can you please check latest patchset i have updated copyright to original so i assume this is done now :)
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/6/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/6/src/soc/intel/common/block/... PS6, Line 20: Curious about some of the legacy devices here:
1. There is a forbidden list that Linux kernel maintains https://github.com/torvalds/linux/blob/master/drivers/acpi/acpi_platform.c#L.... Does it mean that these should not be exposed by the BIOS?
2. There are some HIDs that are not enumerated at all by the kernel. Are these added because they are used by other OSes?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/6/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/6/src/soc/intel/common/block/... PS6, Line 20:
Curious about some of the legacy devices here:
- There is a forbidden list that Linux kernel maintains https://github.com/torvalds/linux/blob/master/drivers/acpi/acpi_platform.c#L.... Does it mean that these should not be exposed by the BIOS?
not sure in which context this "forbidden" word been used in lunux kernel list. But those devices are just added to maintain the legacy support since some time now. Even I was looking at UEFI bios code from could see the same devices.
btw, running cycle test over 2 days now will continue to run this weekend before merging CLs
- There are some HIDs that are not enumerated at all by the kernel. Are these added because they are used by other OSes?
as we are moving towards common code hence added the full supported list but i don't think all OS will bind this full device list
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 6:
can we get a vote here?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 6: Code-Review+2
Patch Set 6:
can we get a vote here?
Looks good, thanks!
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 6:
Patch Set 6: Code-Review+2
Patch Set 6:
can we get a vote here?
Looks good, thanks!
Thanks
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi
This patch creates a common instance of lpc.asl inside intel common code (soc/intel/common/block/acpi/acpi) and asks specific soc code to refer lpc.asl from common code block.
Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI rather than LPC.
TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify Device(LPCB) device presence after booting to OS.
Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36455 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- D src/soc/intel/apollolake/acpi/lpc.asl M src/soc/intel/apollolake/acpi/southbridge.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/cannonlake/acpi/southbridge.asl R src/soc/intel/common/block/acpi/acpi/lpc.asl M src/soc/intel/denverton_ns/acpi/lpc.asl M src/soc/intel/denverton_ns/include/soc/iomap.h D src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/skylake/acpi/lpc.asl 10 files changed, 50 insertions(+), 337 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/apollolake/acpi/lpc.asl b/src/soc/intel/apollolake/acpi/lpc.asl deleted file mode 100644 index 749daf7..0000000 --- a/src/soc/intel/apollolake/acpi/lpc.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel LPC Bus Device - 0:1f.0 */ - -Device (LPCB) -{ - Name (_ADR, 0x001f0000) -} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 7c9c873..9acb9ae 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -33,7 +33,7 @@ #include "xhci.asl"
/* LPC */ -#include "lpc.asl" +#include <soc/intel/common/block/acpi/acpi/lpc.asl>
/* eMMC */ #include "scs.asl" diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 4b82365..3057fbe 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,6 +25,8 @@ #define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE (32 * KiB)
+#define HPET_BASE_ADDRESS 0xfed00000 + #define ACPI_BASE_ADDRESS 0x400 #define ACPI_BASE_SIZE 0x100 #define R_ACPI_PM1_TMR 0x8 diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 8ba3d89..b52de65 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -32,7 +32,7 @@ #endif
/* LPC 0:1f.0 */ -#include "lpc.asl" +#include <soc/intel/common/block/acpi/acpi/lpc.asl>
/* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/cannonlake/acpi/lpc.asl b/src/soc/intel/common/block/acpi/acpi/lpc.asl similarity index 79% rename from src/soc/intel/cannonlake/acpi/lpc.asl rename to src/soc/intel/common/block/acpi/acpi/lpc.asl index f1c1bf3..e7f6660 100644 --- a/src/soc/intel/cannonlake/acpi/lpc.asl +++ b/src/soc/intel/common/block/acpi/acpi/lpc.asl @@ -15,11 +15,29 @@ * GNU General Public License for more details. */
+/* Intel LPC/eSPI Bus Device - 0:1f.0 */ +#include <soc/iomap.h> + Device (LPCB) { Name (_ADR, 0x001f0000) Name (_DDN, "LPC Bus Device")
+ /* DMA Controller */ + Device (DMAC) + { + Name (_HID, EISAID("PNP0200")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } + }) + } + + /* Firmware Hub */ Device (FWH) { Name (_HID, EISAID ("INT0800")) @@ -30,9 +48,11 @@ }) }
+ /* High Precision Event Timer */ Device (HPET) { Name (_HID, EISAID ("PNP0103")) + Name (_CID, 0x010CD041) Name (_DDN, "High Precision Event Timer") Name (_CRS, ResourceTemplate () { @@ -40,10 +60,22 @@ }) Method (_STA, 0) { - Return (0xf) + Return (0xF) } }
+ /* FPU */ + Device(MATH) + { + Name (_HID, EISAID("PNP0C04")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) + IRQNoFlags() { 13 } + }) + } + + /* AT Interrupt Controller */ Device (PIC) { Name (_HID, EISAID ("PNP0000")) @@ -71,6 +103,7 @@ }) }
+ /* LPC device: Resource consumption */ Device (LDRC) { Name (_HID, EISAID ("PNP0C02")) @@ -92,6 +125,7 @@ }) }
+ /* Real Time Clock Device */ Device (RTC) { Name (_HID, EISAID ("PNP0B00")) @@ -102,6 +136,7 @@ }) }
+ /* Timer */ Device (TIMR) { Name (_HID, EISAID ("PNP0100")) @@ -113,5 +148,4 @@ IRQNoFlags () {0} }) } - } diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl index cc36451..4b6e786 100644 --- a/src/soc/intel/denverton_ns/acpi/lpc.asl +++ b/src/soc/intel/denverton_ns/acpi/lpc.asl @@ -16,10 +16,11 @@ */
// Intel LPC Bus Device - 0:1f.0 +#include <soc/intel/common/block/acpi/acpi/lpc.asl>
-Device (LPCB) +Scope (_SB.PCI0.LPCB) { - Name(_ADR, 0x001f0000) + #include "irqlinks.asl"
OperationRegion(LPC0, PCI_Config, 0x00, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) @@ -29,8 +30,6 @@ IOD1, 8, }
- #include "irqlinks.asl" - Device(APIC) // IO APIC { Name(_HID,EISAID("PNP0003")) @@ -40,96 +39,6 @@ }) }
- Device (HPET) - { - Name (_HID, EISAID("PNP0103")) - Name (_CID, 0x010CD041) - - Method (_STA, 0) // Device Status - { - Return (0xF) // Enable and show device - } - - Name(_CRS, ResourceTemplate() - { - Memory32Fixed(ReadOnly, DEFAULT_HPET_ADDR, 0x400) - }) - } - - Device(PIC) // 8259 Interrupt Controller - { - Name(_HID,EISAID("PNP0000")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 2) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x70, 0x70, 0x1, 0x01) // NMI Enable. - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap - - // BIOS ROM shadow memory range - Memory32Fixed(ReadOnly, 0x000E0000, 0x20000) - - // BIOS flash 16MB - Memory32Fixed(ReadOnly,0xFF000000,0x1000000) - }) - } - - Device (RTC) // Real Time Clock - { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } - }) - } - - Device (TIMR) // Intel 8254 timer - { - Name(_HID, EISAID("PNP0100")) - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} - }) - } - Device(IUR3) // Internal UART 1 { Name(_HID, EISAID("PNP0501")) diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index 8bcef91..c512d55 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -31,6 +31,8 @@ #define ACPI_BASE_ADDRESS DEFAULT_PMBASE #define DEFAULT_TCO_BASE 0x400
+#define HPET_BASE_ADDRESS 0xfed00000 + /* Southbridge internal device MEM BARs (Set to match FSP settings) */ #define DEFAULT_PCR_BASE 0xfd000000 #define DEFAULT_PWRM_BASE 0xfe000000 diff --git a/src/soc/intel/icelake/acpi/espi.asl b/src/soc/intel/icelake/acpi/espi.asl deleted file mode 100644 index 4456812..0000000 --- a/src/soc/intel/icelake/acpi/espi.asl +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/* Device identifier is not changed to ESPI to maintain coherency with ec.asl */ -Device (LPCB) -{ - Name (_ADR, 0x001f0000) - Name (_DDN, "ESPI Bus Device") - - Device (FWH) - { - Name (_HID, EISAID ("INT0800")) - Name (_DDN, "Firmware Hub") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID ("PNP0103")) - Name (_DDN, "High Precision Event Timer") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - Method (_STA, 0) - { - Return (0xf) - } - } - - Device (PIC) - { - Name (_HID, EISAID ("PNP0000")) - Name (_DDN, "8259 Interrupt Controller") - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device (LDRC) - { - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 2) - Name (_DDN, "Legacy Device Resources") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, - 0x1, 0xff) - }) - } - - Device (RTC) - { - Name (_HID, EISAID ("PNP0B00")) - Name (_DDN, "Real Time Clock") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x70, 0x70, 1, 8) - }) - } - - Device (TIMR) - { - Name (_HID, EISAID ("PNP0100")) - Name (_DDN, "8254 Timer") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags () {0} - }) - } - -} diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index ffd2fcc..389963e 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -33,7 +33,7 @@ #include "gpio.asl"
/* ESPI 0:1f.0 */ -#include "espi.asl" +#include <soc/intel/common/block/acpi/acpi/lpc.asl>
/* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl index c9167ad..7dd0298 100644 --- a/src/soc/intel/skylake/acpi/lpc.asl +++ b/src/soc/intel/skylake/acpi/lpc.asl @@ -15,105 +15,11 @@ * GNU General Public License for more details. */
-Device (LPCB) +// Intel LPC Bus Device - 0:1f.0 +#include <soc/intel/common/block/acpi/acpi/lpc.asl> + +Scope (_SB.PCI0.LPCB) { - Name (_ADR, 0x001f0000) - Name (_DDN, "LPC Bus Device") - - Device (FWH) - { - Name (_HID, EISAID ("INT0800")) - Name (_DDN, "Firmware Hub") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) - }) - } - - Device (HPET) - { - Name (_HID, EISAID ("PNP0103")) - Name (_DDN, "High Precision Event Timer") - Name (_CRS, ResourceTemplate () - { - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - Method (_STA, 0) - { - Return (0xf) - } - } - - Device (PIC) - { - Name (_HID, EISAID ("PNP0000")) - Name (_DDN, "8259 Interrupt Controller") - Name (_CRS, ResourceTemplate() - { - IO (Decode16, 0x20, 0x20, 0x01, 0x02) - IO (Decode16, 0x24, 0x24, 0x01, 0x02) - IO (Decode16, 0x28, 0x28, 0x01, 0x02) - IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) - IO (Decode16, 0x30, 0x30, 0x01, 0x02) - IO (Decode16, 0x34, 0x34, 0x01, 0x02) - IO (Decode16, 0x38, 0x38, 0x01, 0x02) - IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) - IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) - IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) - IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) - IO (Decode16, 0xac, 0xac, 0x01, 0x02) - IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) - IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) - IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) - IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) - IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) - IRQNoFlags () { 2 } - }) - } - - Device (LDRC) - { - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 2) - Name (_DDN, "Legacy Device Resources") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO - IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, - 0x1, 0xff) - }) - } - - Device (RTC) - { - Name (_HID, EISAID ("PNP0B00")) - Name (_DDN, "Real Time Clock") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x70, 0x70, 1, 8) - }) - } - - Device (TIMR) - { - Name (_HID, EISAID ("PNP0100")) - Name (_DDN, "8254 Timer") - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x40, 0x40, 0x01, 0x04) - IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags () {0} - }) - } - #include <acpi/ec.asl> #include <acpi/superio.asl> }
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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