Change in coreboot[master]: src/southbridge/amd/pi/hudson: add southbridge C bootblock initializa...

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Michał Żygowski (Code Review)

23 Nov 2019 23 Nov '19

5:43 p.m.

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: src/southbridge/amd/pi/hudson: add southbridge C bootblock initialization ......................................................................

src/southbridge/amd/pi/hudson: add southbridge C bootblock initialization

Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af --- M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/hudson.h 3 files changed, 55 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/1

diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 0eccadb..8c47328 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,7 +28,12 @@ # #*****************************************************************************

-bootblock-y += enable_usbdebug.c + +ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +bootblock-y += bootblock.c +bootblock-y += early_setup.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +endif

romstage-y += early_setup.c romstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index f12cec8..d5faeb3 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -60,3 +60,48 @@ { hudson_enable_rom(); } + +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) + +#include <bootblock_common.h> +#include <arch/io.h> +#include <device/pci_ids.h> +#include <southbridge/amd/pi/hudson/hudson.h> + +void bootblock_soc_early_init(void) +{ + pci_devfn_t dev; + u32 data; + + bootblock_southbridge_init(); + hudson_lpc_decode(); + + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding for SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + + /* + * Enable FCH to decode TPM associated Memory and IO regions for vboot + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ + + data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); + data |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xd2, 0xcd6); + outb(0x00, 0xcd7); +} +#endif diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 9511a6a..08adb84 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -117,6 +117,10 @@ #define LPC_ALT_WIDEIO1_ENABLE BIT(2) #define LPC_ALT_WIDEIO0_ENABLE BIT(0)

+#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + #define LPC_WIDEIO2_GENERIC_PORT 0x90

#define SPI_CNTRL0 0x00

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Arthur Heymans (Code Review)

24 Nov 24 Nov

2:50 a.m.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: src/southbridge/amd/pi/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... PS1, Line 31: : ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) guarding should not be needed.

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/bootblock.c:

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... PS1, Line 64: #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) put it in a different file?

Michał Żygowski (Code Review)

4:11 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Hello build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37168

to look at the new patch set (#2).

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af --- M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/hudson.h 7 files changed, 173 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/2

Michał Żygowski (Code Review)

26 Nov 26 Nov

9:35 a.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... PS1, Line 31: : ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)

...

guarding should not be needed.

Compiler may complain on unused static functions then

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/bootblock.c:

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... PS1, Line 64: #if CONFIG(C_ENVIRONMENT_BOOTBLOCK)

...

put it in a different file?

Did not want to duplicate the bootblock_southbridge_init code and break boards that do not have C bootblock

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 26 Nov 2019 09:35:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans arthur@aheymans.xyz Gerrit-MessageType: comment

Kyösti Mälkki (Code Review)

9:43 a.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... PS1, Line 31: : ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)

...

Compiler may complain on unused static functions then

Grep for samples of __unused if you encounter such errors.

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/bootblock.c:

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... PS1, Line 64: #if CONFIG(C_ENVIRONMENT_BOOTBLOCK)

...

Did not want to duplicate the bootblock_southbridge_init code and break boards that do not have C bo […]

Other boards are disabled from build now.

You either create one mammoth commit that changes all the binaryPI boards to C_ENV_BB in one go, or you introduce several transient Kconfig options and probably triple the time of development and review. When we create clean transition with APU2, it's not that hard to repeat the flow on one of the other boards, should some of them survive.

Probably both Pascal and I want preference on VBOOT, not efforts on boards that nobody has tested for several years.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 26 Nov 2019 09:43:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans arthur@aheymans.xyz Comment-In-Reply-To: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-MessageType: comment

Michał Żygowski (Code Review)

11:37 a.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37168

to look at the new patch set (#3).

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/3

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Michał Żygowski (Code Review)

11:41 a.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... PS1, Line 31: : ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)

...

Grep for samples of __unused if you encounter such errors.

Indeed these static functions in bootblock.c are reported as unused, because of how this file was included in ROMCC bootblock. So the guards are needed until I move the binary PI to C bootblock

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/bootblock.c:

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... PS1, Line 64: #if CONFIG(C_ENVIRONMENT_BOOTBLOCK)

...

Other boards are disabled from build now. […]

I also implemented bootblock_soc_early_init for AGESA, that is why I cared for other boards too.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 26 Nov 2019 11:41:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki kyosti.malkki@gmail.com Comment-In-Reply-To: Arthur Heymans arthur@aheymans.xyz Comment-In-Reply-To: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-MessageType: comment

Michał Żygowski (Code Review)

27 Nov 27 Nov

9:09 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37168

to look at the new patch set (#5).

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

TEST=boot PC Engines apu2 with C bootblock patch and launch Debian with Linux kernel 4.14.50

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/5

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Kyösti Mälkki (Code Review)

28 Nov 28 Nov

11:41 a.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... PS5, Line 20: ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) We should make the build work without this guard, I'll have a look.

https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... PS5, Line 108: | DECODE_ENABLE_ADLIB_PORT; The choice made on Intel side was to only open LPC routes for the required devices.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Thu, 28 Nov 2019 11:41:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Michał Żygowski (Code Review)

1:22 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37168

to look at the new patch set (#6).

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/6

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Michał Żygowski (Code Review)

3:28 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... PS5, Line 108: | DECODE_ENABLE_ADLIB_PORT;

...

The choice made on Intel side was to only open LPC routes for the required devices.

Wanted to be as generic as possible to open routes for C bootblock console. I may reduce it to serial ports (1-2) only or something like taht

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Thu, 28 Nov 2019 15:28:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-MessageType: comment

Michał Żygowski (Code Review)

3:29 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37168

to look at the new patch set (#7).

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

TEST=boot PC Engines apu2 with C bootblock patch and launch Debian with Linux kernel 4.14.50

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/7

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Kyösti Mälkki (Code Review)

29 Nov 29 Nov

5 a.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 7:

We can postpone this one in the patch series, not required until CB:36915.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 29 Nov 2019 05:00:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Michał Żygowski (Code Review)

11:50 a.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 7:

...

Patch Set 7:

We can postpone this one in the patch series, not required until CB:36915.

Let me push it before CB:36915. I will also remove the ROMCC_BOOTLBOCK guards.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 29 Nov 2019 11:50:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Kyösti Mälkki (Code Review)

11:54 a.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 7:

...

Patch Set 7:

...
Patch Set 7:

We can postpone this one in the patch series, not required until CB:36915.

Let me push it before CB:36915. I will also remove the ROMCC_BOOTLBOCK guards.

Go ahead, you can replace change-id in CB:37353 too.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 29 Nov 2019 11:54:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Michał Żygowski (Code Review)

11:59 a.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37168

to look at the new patch set (#8).

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Since all board without C bootblock are disabled, add C bootblock southbridge initialization and drop romcc bootblock southbridge Kconfig option.

TEST=boot PC Engines apu2 with C bootblock patch and launch Debian with Linux kernel 4.14.50

Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af --- M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/hudson.h 9 files changed, 148 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/8

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Michał Żygowski (Code Review)

12:02 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37168

to look at the new patch set (#9).

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Since all board without C bootblock are disabled, add C bootblock southbridge initialization and drop romcc bootblock southbridge Kconfig option.

TEST=boot PC Engines apu2 with C bootblock patch and launch Debian with Linux kernel 4.14.50

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/9

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Kyösti Mälkki (Code Review)

11:05 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 9:

We will use patchset #6 with the original change-id. Push #9 with new change-id after ROMCC board disablement CB:37355.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 29 Nov 2019 23:05:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Angel Pons (Code Review)

30 Nov 30 Nov

3:57 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 9:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... PS9, Line 93: = 0 dead assignment

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... PS9, Line 97: tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 This might look better with shorter macro names. As it is, currently, I'd understand an hex number more easily

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Sat, 30 Nov 2019 15:57:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Michał Żygowski (Code Review)

1 Dec 1 Dec

3:21 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 9:

...

Patch Set 9:

We will use patchset #6 with the original change-id. Push #9 with new change-id after ROMCC board disablement CB:37355.

It is currently after CB:37355 in the relation chain. I do not exactly understand what you mean.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Sun, 01 Dec 2019 15:21:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Kyösti Mälkki (Code Review)

4:16 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 9:

...

Patch Set 9:

...
Patch Set 9:

We will use patchset #6 with the original change-id. Push #9 with new change-id after ROMCC board disablement CB:37355.

It is currently after CB:37355 in the relation chain. I do not exactly understand what you mean.

I don't want to land commits to platform code that does not get build-tested. Therefore, I would not disable apu1, g505s or imb-a180h boards at all. Let me know if you have some local work that you have not submitted yet, I'll rearrange the series and see if something else needs to be done.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Sun, 01 Dec 2019 16:16:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Michał Żygowski (Code Review)

5:54 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 9:

...

Patch Set 9:

...
Patch Set 9:

...
Patch Set 9:

We will use patchset #6 with the original change-id. Push #9 with new change-id after ROMCC board disablement CB:37355.

It is currently after CB:37355 in the relation chain. I do not exactly understand what you mean.

I don't want to land commits to platform code that does not get build-tested. Therefore, I would not disable apu1, g505s or imb-a180h boards at all. Let me know if you have some local work that you have not submitted yet, I'll rearrange the series and see if something else needs to be done.

Only fam14 and apu1 have patches for now, see CB:37332

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Sun, 01 Dec 2019 17:54:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Michał Żygowski (Code Review)

2 Dec 2 Dec

2:41 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37168

to look at the new patch set (#10).

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Since all board without C bootblock are disabled, add C bootblock southbridge initialization and drop romcc bootblock southbridge Kconfig option.

TEST=boot PC Engines apu2 with C bootblock patch and launch Debian with Linux kernel 4.14.50

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/10

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Michał Żygowski (Code Review)

5:33 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37168

to look at the new patch set (#11).

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Since all board without C bootblock are disabled, add C bootblock southbridge initialization and drop romcc bootblock southbridge Kconfig option.

TEST=boot PC Engines apu2 with C bootblock patch and launch Debian with Linux kernel 4.14.50

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/11

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Kyösti Mälkki (Code Review)

3 Dec 3 Dec

7:16 a.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Kyösti Mälkki has uploaded a new patch set (#13) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/13

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Kyösti Mälkki (Code Review)

12:45 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 13:

(4 comments)

https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... PS5, Line 20: ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)

...

We should make the build work without this guard, I'll have a look.

Ack

https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/5/src/southbridge/amd/agesa/h... PS5, Line 108: | DECODE_ENABLE_ADLIB_PORT;

...

Wanted to be as generic as possible to open routes for C bootblock console. […]

We can decide on this later. I am not so happy about these long names either.

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... PS1, Line 31: : ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)

...

Indeed these static functions in bootblock. […]

There is a cleanup at the end of patchtrain.

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/bootblock.c:

https://review.coreboot.org/c/coreboot/+/37168/1/src/southbridge/amd/pi/huds... PS1, Line 64: #if CONFIG(C_ENVIRONMENT_BOOTBLOCK)

...

I also implemented bootblock_soc_early_init for AGESA, that is why I cared for other boards too.

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 03 Dec 2019 12:45:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki kyosti.malkki@gmail.com Comment-In-Reply-To: Arthur Heymans arthur@aheymans.xyz Comment-In-Reply-To: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-MessageType: comment

Kyösti Mälkki (Code Review)

12:50 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... PS9, Line 97: tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2

...

This might look better with shorter macro names. […]

I agree. Now that I think of this more, I think common bootblock should only open up the serial port IO and 2e/4e routes to LPC. I am not so eager to use devicetree here, while I know Intel side generally does it now.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 03 Dec 2019 12:50:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

Angel Pons (Code Review)

3:34 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... PS9, Line 97: tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2

...

I agree. […]

Maybe have the mainboards enable the needed LPC decodes in a bootblock.c file?

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 03 Dec 2019 15:34:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki kyosti.malkki@gmail.com Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

Michał Żygowski (Code Review)

4 Dec 4 Dec

1:54 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37168

to look at the new patch set (#14).

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af --- M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/hudson.h 8 files changed, 176 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/14

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

build bot (Jenkins) (Code Review)

1:55 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 14:

(2 comments)

https://review.coreboot.org/c/coreboot/+/37168/14/src/southbridge/amd/agesa/... File src/southbridge/amd/agesa/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/14/src/southbridge/amd/agesa/... PS14, Line 102: tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 trailing whitespace

https://review.coreboot.org/c/coreboot/+/37168/14/src/southbridge/amd/pi/hud... File src/southbridge/amd/pi/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/14/src/southbridge/amd/pi/hud... PS14, Line 135: tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 trailing whitespace

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 04 Dec 2019 13:55:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Michał Żygowski (Code Review)

2:06 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37168

to look at the new patch set (#15).

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af --- M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/hudson.h 8 files changed, 176 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37168/15

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Michał Żygowski (Code Review)

2:29 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 15:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... PS9, Line 93: = 0

...

dead assignment

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 04 Dec 2019 14:29:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

Kyösti Mälkki (Code Review)

4:27 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 16: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 16 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 04 Dec 2019 16:27:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Kyösti Mälkki (Code Review)

4:39 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

Patch Set 16:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... PS9, Line 97: tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2

...

Maybe have the mainboards enable the needed LPC decodes in a bootblock. […]

I find the current solution enabling common serial IOs good enough for now. Note that vendorcode comes into play with LPC decodes aswell.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 16 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 04 Dec 2019 16:39:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki kyosti.malkki@gmail.com Comment-In-Reply-To: Angel Pons th3fanbus@gmail.com Gerrit-MessageType: comment

Kyösti Mälkki (Code Review)

4:39 p.m.

New subject: Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization ......................................................................

sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Reviewed-on: https://review.coreboot.org/c/coreboot/+/37168 Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/hudson.h 8 files changed, 176 insertions(+), 17 deletions(-)

Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved

diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 5cb3755..5c92128 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -17,7 +17,12 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c

-bootblock-y += enable_usbdebug.c +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +bootblock-y += early_setup.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +endif + romstage-y += enable_usbdebug.c ramstage-y += enable_usbdebug.c romstage-y += early_setup.c diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index f12cec8..97e8803 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -60,3 +60,48 @@ { hudson_enable_rom(); } + + +#if !CONFIG(ROMCC_BOOTBLOCK) + +#include <bootblock_common.h> +#include <amdblocks/acpimmio.h> +#include <southbridge/amd/agesa/hudson/hudson.h> + +void bootblock_soc_early_init(void) +{ + pci_devfn_t dev; + u32 data; + + bootblock_southbridge_init(); + hudson_lpc_decode(); + enable_acpimmio_decode_pm24(); + + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding for SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + + /* + * Enable FCH to decode TPM associated Memory and IO regions for vboot + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ + + data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); + data |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + pm_write8(0xd2, 0); +} +#endif diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index c5e6c25..d85cb2b 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -87,4 +87,22 @@ pci_write_config8(dev, 0x4a, byte); }

+void hudson_lpc_decode(void) +{ + pci_devfn_t dev; + u32 tmp; + + dev = PCI_DEV(0, 0x14, 3); + /* Serial port numeration on Hudson: + * PORT0 - 0x3f8 + * PORT1 - 0x2f8 + * PORT5 - 0x2e8 + * PORT7 - 0x3e8 + */ + tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7; + + pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); +} + #endif /* _HUDSON_EARLY_SETUP_C_ */ diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 4927a3a..8a36ea2 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -45,6 +45,46 @@ #define REV_HUDSON_A11 0x11 #define REV_HUDSON_A12 0x12

+#define LPC_IO_PORT_DECODE_ENABLE 0x44 +#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) +#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) +#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) +#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) +#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) +#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) +#define DECODE_ENABLE_SERIAL_PORT0 BIT(6) +#define DECODE_ENABLE_SERIAL_PORT1 BIT(7) +#define DECODE_ENABLE_SERIAL_PORT2 BIT(8) +#define DECODE_ENABLE_SERIAL_PORT3 BIT(9) +#define DECODE_ENABLE_SERIAL_PORT4 BIT(10) +#define DECODE_ENABLE_SERIAL_PORT5 BIT(11) +#define DECODE_ENABLE_SERIAL_PORT6 BIT(12) +#define DECODE_ENABLE_SERIAL_PORT7 BIT(13) +#define DECODE_ENABLE_AUDIO_PORT0 BIT(14) +#define DECODE_ENABLE_AUDIO_PORT1 BIT(15) +#define DECODE_ENABLE_AUDIO_PORT2 BIT(16) +#define DECODE_ENABLE_AUDIO_PORT3 BIT(17) +#define DECODE_ENABLE_MIDI_PORT0 BIT(18) +#define DECODE_ENABLE_MIDI_PORT1 BIT(19) +#define DECODE_ENABLE_MIDI_PORT2 BIT(20) +#define DECODE_ENABLE_MIDI_PORT3 BIT(21) +#define DECODE_ENABLE_MSS_PORT0 BIT(22) +#define DECODE_ENABLE_MSS_PORT1 BIT(23) +#define DECODE_ENABLE_MSS_PORT2 BIT(24) +#define DECODE_ENABLE_MSS_PORT3 BIT(25) +#define DECODE_ENABLE_FDC_PORT0 BIT(26) +#define DECODE_ENABLE_FDC_PORT1 BIT(27) +#define DECODE_ENABLE_GAME_PORT BIT(28) +#define DECODE_ENABLE_KBC_PORT BIT(29) +#define DECODE_ENABLE_ACPIUC_PORT BIT(30) +#define DECODE_ENABLE_ADLIB_PORT BIT(31) + +#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 + +#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + #define SPIROM_BASE_ADDRESS_REGISTER 0xA0 #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 @@ -63,6 +103,7 @@

void hudson_lpc_port80(void); void hudson_pci_port80(void); +void hudson_lpc_decode(void); void hudson_clk_output_48Mhz(void);

void hudson_enable(struct device *dev); diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 0eccadb..615fc04 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,7 +28,11 @@ # #*****************************************************************************

-bootblock-y += enable_usbdebug.c +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +bootblock-y += early_setup.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +endif

romstage-y += early_setup.c romstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index f12cec8..e9a9d33 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -60,3 +60,50 @@ { hudson_enable_rom(); } + +#if !CONFIG(ROMCC_BOOTBLOCK) + +#include <bootblock_common.h> +#include <amdblocks/acpimmio.h> +#include <southbridge/amd/pi/hudson/hudson.h> + +void bootblock_soc_early_init(void) +{ + pci_devfn_t dev; + u32 data; + + bootblock_southbridge_init(); + hudson_lpc_decode(); + if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)) + enable_acpimmio_decode_pm24(); + else + enable_acpimmio_decode_pm04(); + + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding for SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + + /* + * Enable FCH to decode TPM associated Memory and IO regions for vboot + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ + + data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); + data |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + pm_write8(0xd2, 0); +} +#endif diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 3453021..56b894c 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -123,22 +123,17 @@ void hudson_lpc_decode(void) { pci_devfn_t dev; - u32 tmp = 0; + u32 tmp;

- /* Enable I/O decode to LPC bus */ - dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 - | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 - | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 - | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 - | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 - | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 - | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 - | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 - | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 - | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT - | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT - | DECODE_ENABLE_ADLIB_PORT; + dev = PCI_DEV(0, 0x14, 3); + /* Serial port numeration on Hudson: + * PORT0 - 0x3f8 + * PORT1 - 0x2f8 + * PORT5 - 0x2e8 + * PORT7 - 0x3e8 + */ + tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7;

pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); } diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index ac35536..6264319 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -117,6 +117,10 @@ #define LPC_ALT_WIDEIO1_ENABLE BIT(2) #define LPC_ALT_WIDEIO0_ENABLE BIT(0)

+#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + #define LPC_WIDEIO2_GENERIC_PORT 0x90

#define SPI_CNTRL0 0x00

-- To view, visit https://review.coreboot.org/c/coreboot/+/37168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Gerrit-Change-Number: 37168 Gerrit-PatchSet: 17 Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Angel Pons th3fanbus@gmail.com Gerrit-CC: Arthur Heymans arthur@aheymans.xyz Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: merged

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