Change in coreboot[master]: sb/intel/ibexpeak: Use common AHCI library

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47865 )

Change subject: sb/intel/ibexpeak: Use common AHCI library
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sb/intel/ibexpeak: Use common AHCI library

Behaviour before after this patch should be equivalent.

Change-Id: I9b636f093dfaa5954667fe0198e6602e8c1e4943
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/ibexpeak/sata.c
1 file changed, 37 insertions(+), 27 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47865/1

diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 2c6b0ca..20458f5 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -8,6 +8,7 @@
 #include <device/pci_ids.h>
 #include <option.h>
 #include <acpi/acpi_sata.h>
+#include <southbridge/intel/common/ahci.h>
 #include <types.h>

#include "chip.h"
@@ -53,9 +54,6 @@
    		   PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);

if (sata_mode == 0) {
-		/* AHCI */
-		u32 *abar;
-
    	printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");

/* Set Interrupt Line */
@@ -80,31 +78,43 @@
    	pci_write_config32(dev, 0x98, 0x00590200);

/* Initialize AHCI memory-mapped space */
-		abar = (u32 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-		printk(BIOS_DEBUG, "ABAR: %p\n", abar);
-		/* CAP (HBA Capabilities) : enable power management */
-		reg32 = read32(abar + 0x00);
-		reg32 |= 0x0c006000;	// set PSC+SSC+SALP+SSS
-		reg32 &= ~0x00020060;	// clear SXS+EMS+PMS
-		/* Set ISS, if available */
-		if (config->sata_interface_speed_support) {
-			reg32 &= ~0x00f00000;
-			reg32 |= (config->sata_interface_speed_support & 0x03)
-			    << 20;
-		}
-		write32(abar + 0x00, reg32);
-		/* PI (Ports implemented) */
-		write32(abar + 0x03, config->sata_port_map);
-		(void)read32(abar + 0x03);	/* Read back 1 */
-		(void)read32(abar + 0x03);	/* Read back 2 */
-		/* CAP2 (HBA Capabilities Extended) */
-		reg32 = read32(abar + 0x09);
-		reg32 &= ~0x00000002;
-		write32(abar + 0x09, reg32);
-		/* VSP (Vendor Specific Register */
-		reg32 = read32(abar + 0x28);
+		const uintptr_t ahci_bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+		printk(BIOS_DEBUG, "AHCI BAR: %p\n", (void *)ahci_bar);
+
+		union ahci_reg_cap ahci_cap = {
+			.raw = ahci_read32(ahci_bar, AHCI_REG_CAP),
+		};
+
+		ahci_cap.external_sata        = 0; /* TODO: Make this configurable? */
+		ahci_cap.enclosure_management = 0;
+		ahci_cap.port_multiplier      = 0;
+
+		ahci_cap.partial_state        = 1;
+		ahci_cap.slumber_state        = 1;
+		ahci_cap.aggressive_link_pm   = 1;
+		ahci_cap.staggered_spinup     = 1;
+
+		/* If configured, override ISS */
+		if (config->sata_interface_speed_support)
+			ahci_cap.interface_speed = config->sata_interface_speed_support;
+
+		ahci_write32(ahci_bar, AHCI_REG_CAP, ahci_cap.raw);
+
+		ahci_write_ports_implemented(ahci_bar, config->sata_port_map);
+
+		union ahci_reg_cap_2 ahci_cap_2 = {
+			.raw = ahci_read32(ahci_bar, AHCI_REG_CAP_2),
+		};
+
+		ahci_cap_2.nvm_hci_present = 0;
+
+		ahci_write32(ahci_bar, AHCI_REG_CAP_2, ahci_cap_2.raw);
+
+		/* VSP (Vendor Specific Register) */
+		reg32 = ahci_read32(ahci_bar, 0xa0);
    	reg32 &= ~0x00000005;
-		write32(abar + 0x28, reg32);
+		ahci_write32(ahci_bar, 0xa0, reg32);
+
    } else {
    	/* IDE */
    	printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47865 )

Change subject: sb/intel/ibexpeak: Use common AHCI library
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47865/2/src/southbridge/intel/ibexp... 
File src/southbridge/intel/ibexpeak/sata.c:

https://review.coreboot.org/c/coreboot/+/47865/2/src/southbridge/intel/ibexp... 
PS2, Line 81: 		const uintptr_t ahci_bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
this should use probe_resource instead

[M] Change in coreboot[master]: sb/intel/ibexpeak: Use common AHCI library

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47865?usp=email )

Change subject: sb/intel/ibexpeak: Use common AHCI library
......................................................................

Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.