Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38986 )
Change subject: WIP: IIO work ......................................................................
WIP: IIO work
This is work-in-progress, with the goal to identify common parts of IIO-related housekeeping functionality in different Xeons.
Change-Id: I2c459fc5deb885c5f979499b75dc95633bb6c00f Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/cpu/intel/xeonsp/Makefile.inc M src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c A src/cpu/intel/xeonsp/iio.c A src/cpu/intel/xeonsp/include/soc/fsp_hobs.h A src/cpu/intel/xeonsp/include/soc/iio.h 5 files changed, 135 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38986/1
diff --git a/src/cpu/intel/xeonsp/Makefile.inc b/src/cpu/intel/xeonsp/Makefile.inc index e9abf59..c1452f4 100644 --- a/src/cpu/intel/xeonsp/Makefile.inc +++ b/src/cpu/intel/xeonsp/Makefile.inc @@ -21,7 +21,7 @@ bootblock-y += bootblock.c romstage-y += ../../../cpu/intel/car/romstage.c romstage-y += postcar.c romstage.c -ramstage-y += model_xeonsp_init.c lpc.c ramstage.c +ramstage-y += model_xeonsp_init.c lpc.c ramstage.c iio.c
CPPFLAGS_common += -I$(src)/cpu/intel/xeonsp/include
diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c index 10a6855..e5685ab 100644 --- a/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c @@ -21,6 +21,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <device/pci.h> +#include <soc/iio.h>
static void skxsp_pci_domain_read_resources(struct device *dev) { @@ -69,6 +70,7 @@ /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; + attach_iio_stacks(dev); } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; diff --git a/src/cpu/intel/xeonsp/iio.c b/src/cpu/intel/xeonsp/iio.c new file mode 100644 index 0000000..ae721cc --- /dev/null +++ b/src/cpu/intel/xeonsp/iio.c @@ -0,0 +1,93 @@ +#include <assert.h> +#include <soc/hob_mem.h> +#include <soc/hob_iiouds.h> +#include <soc/iio.h> +#include <stdlib.h> + +static void get_iiostack_info(struct iiostack_resource *info) +{ + size_t hob_size; + u8 stack_no; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob; + + memset(info, 0, sizeof(struct iiostack_resource)); + + hob = fsp_find_extension_hob_by_guid( + fsp_hob_iio_universal_data_guid, + &hob_size); + assert(hob != NULL && hob_size != 0); + + // find out total number of stacks + info->no_of_stacks = 0; + info->sres = NULL; + for (int s=0; s < hob->PlatformData.numofIIO; ++s) { + for (int x=0; x < MAX_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? + ++info->no_of_stacks; + } + } + assert(info->no_of_stacks > 0); + + // allocate and copy stack info from FSP HOB + info->sres = malloc(info->no_of_stacks * sizeof(STACK_RES)); + if (info->sres == 0) + die("build_stack_info(): out of memory.\n"); + memset(info->sres, 0, info->no_of_stacks * sizeof(STACK_RES)); + + stack_no = 0; + for (int s=0; s < hob->PlatformData.numofIIO; ++s) { + for (int x=0; x < MAX_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? + memcpy(&info->sres[stack_no++], ri, sizeof(STACK_RES)); + } + } +} + + +/* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ +void attach_iio_stacks(struct device *dev) +{ + struct bus *iiostack_bus; + struct device dummy; + struct iiostack_resource stack_info; + + get_iiostack_info(&stack_info); + for (int s=0; s < stack_info.no_of_stacks; ++s) { + printk(BIOS_DEBUG, "Attaching stack 0x%x to device %s\n", stack_info.sres[s].BusBase, dev_path(dev)); + if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */ + continue; + + iiostack_bus = malloc(sizeof(struct bus)); + if (iiostack_bus == 0) + die("attach_iio_stacks(): out of memory.\n"); + memset(iiostack_bus, 0, sizeof(struct bus)); + memcpy(iiostack_bus, dev->bus, sizeof(struct bus)); + iiostack_bus->secondary = stack_info.sres[s].BusBase; + iiostack_bus->subordinate = stack_info.sres[s].BusBase; + iiostack_bus->dev = NULL; + iiostack_bus->children = NULL; + iiostack_bus->next = NULL; + iiostack_bus->link_num = 1; + + dummy.bus = iiostack_bus; + dummy.path.type = DEVICE_PATH_PCI; + dummy.path.pci.devfn = 0; + u32 id = pci_read_config32(&dummy, PCI_VENDOR_ID); + if (id == 0xffffffff) + printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy)); + + if (dev->link_list == NULL) { + dev->link_list = iiostack_bus; + } + else { + struct bus *nlink = dev->link_list; + while (nlink->next != NULL) + nlink = nlink->next; + nlink->next = iiostack_bus; + } + } +} + diff --git a/src/cpu/intel/xeonsp/include/soc/fsp_hobs.h b/src/cpu/intel/xeonsp/include/soc/fsp_hobs.h new file mode 100644 index 0000000..fc9edbb --- /dev/null +++ b/src/cpu/intel/xeonsp/include/soc/fsp_hobs.h @@ -0,0 +1,25 @@ +#ifndef _FSP_HOBS_H_ +#define _FSP_HOBS_H_ + +#include <fsp/util.h> +#include <soc/hob_mem.h> +#include <soc/hob_iiouds.h> + +#define MAX_IIO_STACK 6 +#define MAX_KTI_PORTS 3 +#define MAX_SOCKET 2 +#define NUMBER_PORTS_PER_SOCKET 21 +#define MaxIIO MAX_SOCKET +#define CONFIG_TDP_MAX_LEVEL 5 +#define MAX_IMC 2 +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) +#define MAX_TAD_RULES 20 +#define MAX_TAD_WAYS 3 +#define SAD_RULES 24 + +#define FSP_HOB_IIO_UNIVERSAL_DATA_GUID { \ + 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \ + 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \ +} + +#endif diff --git a/src/cpu/intel/xeonsp/include/soc/iio.h b/src/cpu/intel/xeonsp/include/soc/iio.h new file mode 100644 index 0000000..12a8dd3 --- /dev/null +++ b/src/cpu/intel/xeonsp/include/soc/iio.h @@ -0,0 +1,14 @@ +#ifndef SOC_IIO_H +#define SOC_IIO_H + +#include <device/pci.h> +#include <soc/fsp_hobs.h> + +struct iiostack_resource { + uint8_t no_of_stacks; + STACK_RES *sres; +}; + +void attach_iio_stacks(struct device *dev); + +#endif \ No newline at end of file
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38986 )
Change subject: WIP: IIO work ......................................................................
Patch Set 1:
(15 comments)
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c File src/cpu/intel/xeonsp/iio.c:
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c@... PS1, Line 24: for (int s=0; s < hob->PlatformData.numofIIO; ++s) { spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c@... PS1, Line 25: for (int x=0; x < MAX_IIO_STACK; ++x) { spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c@... PS1, Line 27: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c@... PS1, Line 40: for (int s=0; s < hob->PlatformData.numofIIO; ++s) { spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c@... PS1, Line 41: for (int x=0; x < MAX_IIO_STACK; ++x) { spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c@... PS1, Line 43: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c@... PS1, Line 58: for (int s=0; s < stack_info.no_of_stacks; ++s) { spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c@... PS1, Line 59: printk(BIOS_DEBUG, "Attaching stack 0x%x to device %s\n", stack_info.sres[s].BusBase, dev_path(dev)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c@... PS1, Line 60: if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c@... PS1, Line 65: die("attach_iio_stacks(): out of memory.\n"); Prefer using '"%s...", __func__' to using 'attach_iio_stacks', this function's name, in a string
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c@... PS1, Line 80: printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/iio.c@... PS1, Line 85: else { else should follow close brace '}'
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/includ... File src/cpu/intel/xeonsp/include/soc/fsp_hobs.h:
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/includ... PS1, Line 21: 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \ please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/includ... PS1, Line 22: 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \ please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/includ... File src/cpu/intel/xeonsp/include/soc/iio.h:
https://review.coreboot.org/c/coreboot/+/38986/1/src/cpu/intel/xeonsp/includ... PS1, Line 14: #endif adding a line without newline at end of file
Hello Patrick Rudolph, Rocky Phagura, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38986
to look at the new patch set (#2).
Change subject: WIP: IIO work ......................................................................
WIP: IIO work
This is work-in-progress, with the goal to identify common parts of IIO-related housekeeping functionality in different Xeons. We also try to hook up the common iio code into skylake-sp.
Change-Id: I2c459fc5deb885c5f979499b75dc95633bb6c00f Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/cpu/intel/xeonsp/Makefile.inc M src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c A src/cpu/intel/xeonsp/iio.c A src/cpu/intel/xeonsp/include/soc/fsp_hobs.h A src/cpu/intel/xeonsp/include/soc/iio.h 5 files changed, 139 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38986/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38986 )
Change subject: WIP: IIO work ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38986/2/src/cpu/intel/xeonsp/includ... File src/cpu/intel/xeonsp/include/soc/fsp_hobs.h:
https://review.coreboot.org/c/coreboot/+/38986/2/src/cpu/intel/xeonsp/includ... PS2, Line 21: 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \ please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/38986/2/src/cpu/intel/xeonsp/includ... PS2, Line 22: 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \ please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/38986/2/src/cpu/intel/xeonsp/includ... File src/cpu/intel/xeonsp/include/soc/iio.h:
https://review.coreboot.org/c/coreboot/+/38986/2/src/cpu/intel/xeonsp/includ... PS2, Line 14: #endif adding a line without newline at end of file
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38986 )
Change subject: WIP: IIO work ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38986/3/src/cpu/intel/xeonsp/includ... File src/cpu/intel/xeonsp/include/soc/fsp_hobs.h:
https://review.coreboot.org/c/coreboot/+/38986/3/src/cpu/intel/xeonsp/includ... PS3, Line 21: 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \ please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/38986/3/src/cpu/intel/xeonsp/includ... PS3, Line 22: 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \ please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/38986/3/src/cpu/intel/xeonsp/includ... File src/cpu/intel/xeonsp/include/soc/iio.h:
https://review.coreboot.org/c/coreboot/+/38986/3/src/cpu/intel/xeonsp/includ... PS3, Line 14: #endif adding a line without newline at end of file
Hello Patrick Rudolph, Rocky Phagura, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38986
to look at the new patch set (#4).
Change subject: WIP: IIO work ......................................................................
WIP: IIO work
This is work-in-progress, with the goal to identify common parts of IIO-related housekeeping functionality in different Xeons. We also try to hook up the common iio code into skylake-sp.
Change-Id: I2c459fc5deb885c5f979499b75dc95633bb6c00f Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/cpu/intel/xeonsp/Makefile.inc M src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c M src/cpu/intel/xeonsp/cpu/skylake-sp/uncore.c A src/cpu/intel/xeonsp/iio.c A src/cpu/intel/xeonsp/include/soc/fsp_hobs.h A src/cpu/intel/xeonsp/include/soc/iio.h 6 files changed, 198 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38986/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38986 )
Change subject: WIP: IIO work ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38986/4/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38986/4/src/cpu/intel/xeonsp/cpu/sk... PS4, Line 278: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), trailing whitespace
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38986 )
Change subject: WIP: IIO work ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38986/5/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38986/5/src/cpu/intel/xeonsp/cpu/sk... PS5, Line 278: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), trailing whitespace
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38986 )
Change subject: WIP: IIO work ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38986/6/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38986/6/src/cpu/intel/xeonsp/cpu/sk... PS6, Line 278: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), trailing whitespace
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38986 )
Change subject: WIP: IIO work ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38986/7/src/cpu/intel/xeonsp/cpu/sk... File src/cpu/intel/xeonsp/cpu/skylake-sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38986/7/src/cpu/intel/xeonsp/cpu/sk... PS7, Line 278: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), trailing whitespace
Hello Patrick Rudolph, Rocky Phagura, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38986
to look at the new patch set (#8).
Change subject: WIP: xeonsp: Add common IIO-related code ......................................................................
WIP: xeonsp: Add common IIO-related code
Add code that is hopefully common across various Xeon-SP related processors.
This patch is a piece of CB:38549
Change-Id: I2c459fc5deb885c5f979499b75dc95633bb6c00f Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/cpu/intel/xeonsp/Makefile.inc A src/cpu/intel/xeonsp/iio.c A src/cpu/intel/xeonsp/include/soc/fsp_hobs.h A src/cpu/intel/xeonsp/include/soc/iio.h 4 files changed, 638 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38986/8
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38986 )
Change subject: WIP: xeonsp: Add common IIO-related code ......................................................................
Patch Set 8:
(2 comments)
Intel document Reference Number: 329595-002 seems to cover a few registers, but no implementation details.
https://review.coreboot.org/c/coreboot/+/38986/8/src/cpu/intel/xeonsp/iio.c File src/cpu/intel/xeonsp/iio.c:
https://review.coreboot.org/c/coreboot/+/38986/8/src/cpu/intel/xeonsp/iio.c@... PS8, Line 394: static void get_iiostack_info(struct iiostack_resource *info) why is this data read from FSP instead of devicetree or PCI space?
https://review.coreboot.org/c/coreboot/+/38986/8/src/cpu/intel/xeonsp/iio.c@... PS8, Line 534: n isn't a "stack" simply an MMCONF address area or a subregion of that?
Hello Patrick Rudolph, Rocky Phagura, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38986
to look at the new patch set (#9).
Change subject: WIP: xeonsp: Add common IIO-related code ......................................................................
WIP: xeonsp: Add common IIO-related code
Add code that is hopefully common across various Xeon-SP related processors.
This patch is a piece of CB:38549
Change-Id: I2c459fc5deb885c5f979499b75dc95633bb6c00f Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/cpu/intel/xeonsp/Makefile.inc A src/cpu/intel/xeonsp/iio.c A src/cpu/intel/xeonsp/include/soc/fsp_hobs.h A src/cpu/intel/xeonsp/include/soc/iio.h 4 files changed, 638 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38986/9
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38986 )
Change subject: WIP: xeonsp: Add common IIO-related code ......................................................................
Patch Set 10:
(2 comments)
The registers are relatively easy to get from EDS. In a nutshell we need to configure interleaved MMCFG decoder, assign bus number across different sockets (for that we need to either hardcode sockets number and topology or discover it programmatically).
https://review.coreboot.org/c/coreboot/+/38986/8/src/cpu/intel/xeonsp/iio.c File src/cpu/intel/xeonsp/iio.c:
https://review.coreboot.org/c/coreboot/+/38986/8/src/cpu/intel/xeonsp/iio.c@... PS8, Line 394: static void get_iiostack_info(struct iiostack_resource *info)
why is this data read from FSP instead of devicetree or PCI space?
I would think it shouldn't be possible to relay on FSP for this. We should be able to derive all these parameters based from topology of a given system (e.g sockets number and interconnect). In this case, we let FSP figure it all out on its own and populate the HOBs. Right now I have but cursory understanding of it.
https://review.coreboot.org/c/coreboot/+/38986/8/src/cpu/intel/xeonsp/iio.c@... PS8, Line 534: n
isn't a "stack" simply an MMCONF address area or a subregion of that?
so IIO is split into multiple units called "stacks". Each stack behaves as a root port and resides on its own physical bus. I am not quite sure but it may be that these stacks resemble "pci segment groups". These are, in turn, are just another dimension to bus/device/function so it is segment/bus/device/function. All of that is needed because 256 bues is not enough if you have a system with several sockets and you want every one of them to be able to access local MMCONF regions
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38986 )
Change subject: WIP: xeonsp: Add common IIO-related code ......................................................................
Patch Set 10: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/38986/10/src/cpu/intel/xeonsp/iio.c File src/cpu/intel/xeonsp/iio.c:
https://review.coreboot.org/c/coreboot/+/38986/10/src/cpu/intel/xeonsp/iio.c... PS10, Line 24: static void assign_bridge_resources(struct iiostack_resource *stack_list, nit: maybe add a blank line between these two declarations
https://review.coreboot.org/c/coreboot/+/38986/10/src/cpu/intel/xeonsp/iio.c... PS10, Line 430: bux bus
https://review.coreboot.org/c/coreboot/+/38986/10/src/cpu/intel/xeonsp/iio.c... PS10, Line 451: die("%s: out of memory.\n", __func__); lol, that would be hilarious
Andrey Petrov has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38986 )
Change subject: WIP: xeonsp: Add common IIO-related code ......................................................................
Abandoned
killing in favor of new patchset
-
Andrey Petrov (Code Review) -
Angel Pons (Code Review)
-
build bot (Jenkins) (Code Review)
-
Patrick Rudolph (Code Review)