Change in coreboot[master]: soc/intel/alderlake: Update PMC Descriptor for Alderlake B0 silicon

[Paul Menzel (Code Review)]

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55254 )

Change subject: soc/intel/alderlake: Update PMC Descriptor for Alderlake B0 silicon
......................................................................

Patch Set 5:

(6 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/55254/comment/f73802c7_c680d169 
PS5, Line 7: Alderlake
Alder Lake

https://review.coreboot.org/c/coreboot/+/55254/comment/0e99143e_79e91589 
PS5, Line 13: not updated.
Please add the output of the new messages.

File src/soc/intel/alderlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/55254/comment/79b95a8c_46e2051b 
PS5, Line 38: #define GLOBAL_RESET_IS_NOT_REQUIRED      2
Align numbers with tabs as above?

https://review.coreboot.org/c/coreboot/+/55254/comment/31ebd89d_ac69ae13 
PS5, Line 132: int8_t
Why? Please use generic types if not otherwise necessary. Also below.

https://review.coreboot.org/c/coreboot/+/55254/comment/3098f30e_e0b5755e 
PS5, Line 142: uint8_t
Ditto.

https://review.coreboot.org/c/coreboot/+/55254/comment/19a41ff7_961ebbff 
PS5, Line 155: 	if (si_desc_buf[PMC_DESC_7_BYTE3]  == 0x44) {
One space before ==.