[S] Change in coreboot[master]: soc/amd/mendocino: Add UPDs for DPTC current limits - coreboot-gerrit

22 Mar 2023


      Attention is currently required from: Jason Glenesk, Raul Rangel, Fred Reitberger, Patrick Huang.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73875 )
Change subject: soc/amd/mendocino: Add UPDs for DPTC current limits
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Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73875/comment/c41d668b_6465bf0d 
PS3, Line 10: aligned
The struct is packed and the new entries are not aligned. What do you mean?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Iacf0ce0d51d4c8698ec1ae7e810fd00574deeadb
Gerrit-Change-Number: 73875
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