Change in coreboot[master]: autoport: recognize Xeon E3-1200 v2 series memory controllers as sand...
Jonathan Kollasch has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38345 )
Change subject: autoport: recognize Xeon E3-1200 v2 series memory controllers as sandybridge ......................................................................
autoport: recognize Xeon E3-1200 v2 series memory controllers as sandybridge
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: Ic5f18669a04397f570d49c1ff056cd90b3eb04a1 --- M util/autoport/sandybridge.go 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/38345/1
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 718fbe8..acfda6b 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -126,6 +126,7 @@ RegisterPCI(0x8086, 0x0104, sandybridgemc{}) RegisterPCI(0x8086, 0x0150, sandybridgemc{}) RegisterPCI(0x8086, 0x0154, sandybridgemc{}) + RegisterPCI(0x8086, 0x0158, sandybridgemc{}) for _, id := range []uint16{ 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126,
Jonathan Kollasch has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/38345 )
Change subject: autoport: recognize Xeon E3-1200 v2 memory controller as sandybridge ......................................................................
autoport: recognize Xeon E3-1200 v2 memory controller as sandybridge
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: Ic5f18669a04397f570d49c1ff056cd90b3eb04a1 --- M util/autoport/sandybridge.go 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/38345/2
Idwer Vollering has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38345 )
Change subject: autoport: recognize Xeon E3-1200 v2 memory controller as sandybridge ......................................................................
Patch Set 2: Code-Review+2
Idwer Vollering has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38345 )
Change subject: autoport: recognize Xeon E3-1200 v2 memory controller as sandybridge ......................................................................
Patch Set 2:
https://pci-ids.ucw.cz/read/PC/8086/0158
Jonathan Kollasch has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38345 )
Change subject: autoport: recognize Xeon E3-1200 v2 memory controller as sandybridge ......................................................................
Patch Set 2:
Patch Set 2:
What about it?
Idwer Vollering has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38345 )
Change subject: autoport: recognize Xeon E3-1200 v2 memory controller as sandybridge ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
What about it?
Nothing, this was just for proof(tm)/future reference.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38345 )
Change subject: autoport: recognize Xeon E3-1200 v2 memory controller as sandybridge ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/38345/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38345/2//COMMIT_MSG@7 PS2, Line 7: recognize Xeon E3-1200 v2 memory controller as sandybridge Might be a bit long. How about:
Add Xeon E3-1200 v2 memory controller ID
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38345 )
Change subject: autoport: recognize Xeon E3-1200 v2 memory controller as sandybridge ......................................................................
Patch Set 2: Code-Review+1
Hello Angel Pons, Idwer Vollering, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38345
to look at the new patch set (#3).
Change subject: autoport: Add Xeon E3-1200 v2 memory controller ID ......................................................................
autoport: Add Xeon E3-1200 v2 memory controller ID
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: Ic5f18669a04397f570d49c1ff056cd90b3eb04a1 --- M util/autoport/sandybridge.go 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/38345/3
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38345 )
Change subject: autoport: Add Xeon E3-1200 v2 memory controller ID ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38345/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38345/2//COMMIT_MSG@7 PS2, Line 7: recognize Xeon E3-1200 v2 memory controller as sandybridge
Might be a bit long. How about: […]
Done
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38345 )
Change subject: autoport: Add Xeon E3-1200 v2 memory controller ID ......................................................................
autoport: Add Xeon E3-1200 v2 memory controller ID
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: Ic5f18669a04397f570d49c1ff056cd90b3eb04a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38345 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Idwer Vollering vidwer@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M util/autoport/sandybridge.go 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Idwer Vollering: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 718fbe8..acfda6b 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -126,6 +126,7 @@ RegisterPCI(0x8086, 0x0104, sandybridgemc{}) RegisterPCI(0x8086, 0x0150, sandybridgemc{}) RegisterPCI(0x8086, 0x0154, sandybridgemc{}) + RegisterPCI(0x8086, 0x0158, sandybridgemc{}) for _, id := range []uint16{ 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126,
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38345 )
Change subject: autoport: Add Xeon E3-1200 v2 memory controller ID ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : No test failed. EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : No test failed. EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : No test failed.
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Felix Held (Code Review)
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Idwer Vollering (Code Review)
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Jonathan Kollasch (Code Review)
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Paul Menzel (Code Review)