Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36900 )
Change subject: mb/sapphire/pureplatinumh61: Don't write BUC and beyond ......................................................................
mb/sapphire/pureplatinumh61: Don't write BUC and beyond
The BUC register is actually only 16 bits wide and setting bit 5 (disabling GbE) is already done by generic code.
Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/sapphire/pureplatinumh61/early_init.c 1 file changed, 0 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/36900/1
diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index be66561..9a1b685 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -26,11 +26,6 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); }
-void mainboard_late_rcba_config(void) -{ - /* Disable devices. */ - RCBA32(0x3414) = 0x00000020; -} const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 },
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36900 )
Change subject: mb/sapphire/pureplatinumh61: Don't write BUC and beyond ......................................................................
Patch Set 1: Code-Review+2
Hello Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36900
to look at the new patch set (#2).
Change subject: mb/sapphire/pureplatinumh61: Don't write BUC and beyond ......................................................................
mb/sapphire/pureplatinumh61: Don't write BUC and beyond
The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code.
Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/sapphire/pureplatinumh61/early_init.c 1 file changed, 0 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/36900/2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36900 )
Change subject: mb/sapphire/pureplatinumh61: Don't write BUC and beyond ......................................................................
mb/sapphire/pureplatinumh61: Don't write BUC and beyond
The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code.
Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a Signed-off-by: Nico Huber nico.h@gmx.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/36900 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/sapphire/pureplatinumh61/early_init.c 1 file changed, 0 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index be66561..9a1b685 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -26,11 +26,6 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); }
-void mainboard_late_rcba_config(void) -{ - /* Disable devices. */ - RCBA32(0x3414) = 0x00000020; -} const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 0, 0 },
-
Arthur Heymans (Code Review) -
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)