Rasheed Hsueh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45064 )
Change subject: mb/google/volteer/variant/lindar: Update memory settings. ......................................................................
mb/google/volteer/variant/lindar: Update memory settings.
Based on the Lindar's schematic, generate memory settings.
util: rename lp4x spds to include "lp4x-" in name
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: rasheed.hsueh rasheed.hsueh@lcfc.corp-partner.google.com Change-Id: I1ec35d62f8ed21356329b78a614114edad78c2bc --- M src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/memory.c A src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc A src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt 5 files changed, 75 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/45064/1
diff --git a/src/mainboard/google/volteer/variants/lindar/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/Makefile.inc index 776c4ea..b0bfc56 100644 --- a/src/mainboard/google/volteer/variants/lindar/Makefile.inc +++ b/src/mainboard/google/volteer/variants/lindar/Makefile.inc @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only
- bootblock-y += gpio.c
+romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/lindar/memory.c b/src/mainboard/google/volteer/variants/lindar/memory.c new file mode 100644 index 0000000..11bcf4c --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct lpddr4x_cfg lindar_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &lindar_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc new file mode 100644 index 0000000..8c96e06 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt new file mode 100644 index 0000000..9bf0bd9 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt @@ -0,0 +1,2 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCL 0 (0000) diff --git a/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt new file mode 100644 index 0000000..a226d2f --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt @@ -0,0 +1 @@ +K4U6E3S4AA-MGCL
Rasheed Hsueh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45064 )
Change subject: mb/google/volteer/variant/lindar: Update memory settings. ......................................................................
Set Ready For Review
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45064 )
Change subject: mb/google/volteer/variant/lindar: Update memory settings. ......................................................................
Patch Set 1: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45064 )
Change subject: mb/google/volteer/variant/lindar: Update memory settings. ......................................................................
Patch Set 1: Code-Review+2
Yup, looks good now
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45064 )
Change subject: mb/google/volteer/variant/lindar: Update memory settings. ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45064/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45064/1//COMMIT_MSG@2 PS1, Line 2: rasheed.hsueh Please format it like *Rasheed Hsueh*.
$ git config --global user.name "Rasheed Hsueh" $ git commit --amend --author="Rasheed Hsueh rasheed.hsueh@lcfc.corp-partner.google.com"
https://review.coreboot.org/c/coreboot/+/45064/1//COMMIT_MSG@7 PS1, Line 7: mb/google/volteer/variant/lindar: Update memory settings. Please remove the dot/period at the end of the commit message summary.
https://review.coreboot.org/c/coreboot/+/45064/1//COMMIT_MSG@16 PS1, Line 16: rasheed.hsueh Ditto.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Caveh Jalali, Nick Vaccaro, Michael Niewöhner, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45064
to look at the new patch set (#2).
Change subject: mb/google/volteer/variant/lindar: Update memory settings ......................................................................
mb/google/volteer/variant/lindar: Update memory settings
Based on the Lindar's schematic, generate memory settings.
util: rename lp4x spds to include "lp4x-" in name
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Rasheed Hsueh rasheed.hsueh@lcfc.corp-partner.google.com Change-Id: I1ec35d62f8ed21356329b78a614114edad78c2bc --- M src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/memory.c A src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc A src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt 5 files changed, 75 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/45064/2
Rasheed Hsueh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45064 )
Change subject: mb/google/volteer/variant/lindar: Update memory settings ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45064/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45064/1//COMMIT_MSG@2 PS1, Line 2: rasheed.hsueh
Please format it like *Rasheed Hsueh*. […]
Done
https://review.coreboot.org/c/coreboot/+/45064/1//COMMIT_MSG@7 PS1, Line 7: mb/google/volteer/variant/lindar: Update memory settings.
Please remove the dot/period at the end of the commit message summary.
Done
https://review.coreboot.org/c/coreboot/+/45064/1//COMMIT_MSG@16 PS1, Line 16: rasheed.hsueh
Ditto.
Done
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45064 )
Change subject: mb/google/volteer/variant/lindar: Update memory settings ......................................................................
mb/google/volteer/variant/lindar: Update memory settings
Based on the Lindar's schematic, generate memory settings.
util: rename lp4x spds to include "lp4x-" in name
BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Rasheed Hsueh rasheed.hsueh@lcfc.corp-partner.google.com Change-Id: I1ec35d62f8ed21356329b78a614114edad78c2bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45064 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Michael Niewöhner --- M src/mainboard/google/volteer/variants/lindar/Makefile.inc A src/mainboard/google/volteer/variants/lindar/memory.c A src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc A src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt 5 files changed, 75 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/lindar/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/Makefile.inc index 776c4ea..b0bfc56 100644 --- a/src/mainboard/google/volteer/variants/lindar/Makefile.inc +++ b/src/mainboard/google/volteer/variants/lindar/Makefile.inc @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only
- bootblock-y += gpio.c
+romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/lindar/memory.c b/src/mainboard/google/volteer/variants/lindar/memory.c new file mode 100644 index 0000000..11bcf4c --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct lpddr4x_cfg lindar_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &lindar_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc new file mode 100644 index 0000000..8c96e06 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL diff --git a/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt new file mode 100644 index 0000000..9bf0bd9 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt @@ -0,0 +1,2 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCL 0 (0000) diff --git a/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt new file mode 100644 index 0000000..a226d2f --- /dev/null +++ b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt @@ -0,0 +1 @@ +K4U6E3S4AA-MGCL
-
Caveh Jalali (Code Review) -
Michael Niewöhner (Code Review)
-
Paul Menzel (Code Review)
-
Rasheed Hsueh (Code Review)