Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 )

Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports
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Patch Set 25:
> Patch Set 25:
> > Patch Set 25:
> >
> > Do you think that L1 substates should be guarded by that Kconfig?
>
> it wouldn't hurt to add 'CONFIG(PCIEXP_L1_SUB_STATE) &&' to the front of the if statement

That's not the config that I meant. As Nico said, coreboot can enable L1 substates if the FSP says that it's capable. We can use this UPD to get finer-grained control over which devices have L1SS enabled. This may be useful if, for example, only one devices misbehaves with L1SS. In other words, as I understand it, "PCIEXP_L1_SUB_STATE" depends on the FSP UPD (per root-port).
> One dependency for L1 substates is clock PM

Should L1SS be guarded by PCIEXP_CLK_PM?