[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines

[Cliff Huang (Code Review)]

Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )

Change subject: soc/intel/ptl: Add GPE1 defines
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Patch Set 9:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84297/comment/e9e1c6e0_84be7ad0?usp... :
PS9, Line 7: Add GPE1 defines
> Maybe: […]

Done

https://review.coreboot.org/c/coreboot/+/84297/comment/70914e11_ada21f20?usp... :
PS9, Line 9: defines for GPE number for additional STD GPE0 in PTL
           : defines for GPE number for GPE1
           : defines for GPE1 bits
> Please elaborate more before this is submitted.

Done

https://review.coreboot.org/c/coreboot/+/84297/comment/6707ec2c_00cc2f5b?usp... :
PS9, Line 12: STD
> STD GPE have been used for Intel's GPE bits in this case. I can add more here.

Done