HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39029 )
Change subject: src: capitalize 'RAM' ......................................................................
src: capitalize 'RAM'
Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/cpu/intel/microcode/Kconfig M src/drivers/intel/fsp1_1/exit_car.S M src/drivers/intel/fsp2_0/Kconfig M src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex M src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex M src/mainboard/hp/snb_ivb_laptops/Makefile.inc M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/soc/intel/apollolake/glk_page_map.txt M src/soc/intel/denverton_ns/Kconfig 15 files changed, 21 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/39029/1
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index d7d636e..ca72734 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -156,8 +156,8 @@ /* Marker to report base_time. */ { 0, "1st timestamp" }, { TS_START_ROMSTAGE, "start of romstage" }, - { TS_BEFORE_INITRAM, "before ram initialization" }, - { TS_AFTER_INITRAM, "after ram initialization" }, + { TS_BEFORE_INITRAM, "before RAM initialization" }, + { TS_AFTER_INITRAM, "after RAM initialization" }, { TS_END_ROMSTAGE, "end of romstage" }, { TS_START_VBOOT, "start of verified boot" }, { TS_END_VBOOT, "end of verified boot" }, diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 238aad7..c7bbecb 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -4,4 +4,4 @@ default y help Select this option if you want to update the microcode - during the cache as ram setup. + during the cache as RAM setup. diff --git a/src/drivers/intel/fsp1_1/exit_car.S b/src/drivers/intel/fsp1_1/exit_car.S index 4b2822a..a8db68a 100644 --- a/src/drivers/intel/fsp1_1/exit_car.S +++ b/src/drivers/intel/fsp1_1/exit_car.S @@ -17,7 +17,7 @@ chipset_teardown_car:
pop %ebx - /* Move the stack pointer to real ram */ + /* Move the stack pointer to real RAM */ movl post_car_stack_top, %esp /* Align the stack 16 bytes */ andl $0xfffffff0, %esp diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index a8b3ac4..2d45343 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -61,7 +61,7 @@ and FSP_FD_PATH correctly so FSP splitting works.
config FSP_T_FILE - string "Intel FSP-T (temp ram init) binary path and filename" + string "Intel FSP-T (temp RAM init) binary path and filename" depends on FSP_CAR default "$(obj)/Fsp_T.fd" if FSP_USE_REPO help diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex index 111310a..f3e3e75 100644 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex @@ -15,7 +15,7 @@ # GNU General Public License for more details.
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC -# BAP ODE E20XX has 2GB ram soldered down on the Q7 +# BAP ODE E20XX has 2GB RAM soldered down on the Q7 # Memory setting for DDR-1066
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex index ba3d5ac..6e90bfa 100644 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex @@ -15,7 +15,7 @@ # GNU General Public License for more details.
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC -# BAP ODE E20XX has 2GB ram soldered down on the Q7 +# BAP ODE E20XX has 2GB RAM soldered down on the Q7 # Memory setting for DDR-800
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc index d949ad8..50cea25 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc +++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc @@ -20,5 +20,5 @@ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
-# FIXME: Other variants with same size onboard ram may exist. +# FIXME: Other variants with same size onboard RAM may exist. SPD_SOURCES = hynix_4g diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index d34820e..33abc51 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -133,8 +133,8 @@ { uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 5414120..83157d8 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -99,8 +99,8 @@ { uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 0aa70cd..9fde9f7 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -149,8 +149,8 @@ { uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 6ebd7e0..0784c11 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -58,12 +58,12 @@
top_of_ram = (uintptr_t)cbmem_top(); /* Cache 8MiB below the top of ram. On sandybridge systems the top of - * ram under 4GiB is the start of the TSEG region. It is required to + * RAM under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later * for ramstage before setting up the entire RAM as cacheable. */ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
- /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems + /* Cache 8MiB at the top of ram. Top of RAM on sandybridge systems * is where the TSEG region resides. However, it is not restricted * to SMM mode until SMM has been relocated. By setting the region * to cacheable it provides faster access when relocating the SMM diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 1924ddf..334e6c7 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -144,8 +144,8 @@ { uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index dd48d8a..1e871c7 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1636,7 +1636,7 @@ dual_channel_size = MIN(size_ch0, size_ch1) * 2; } else { if (size_ch0 == 0) { - /* ME needs ram on CH0 */ + /* ME needs RAM on CH0 */ size_me = 0; /* TOTEST: bailout? */ } else { diff --git a/src/soc/intel/apollolake/glk_page_map.txt b/src/soc/intel/apollolake/glk_page_map.txt index e96a2db..1a5f11f 100644 --- a/src/soc/intel/apollolake/glk_page_map.txt +++ b/src/soc/intel/apollolake/glk_page_map.txt @@ -1,7 +1,7 @@ 0x00000000, 0x100000000, WB, # RAM # Above entry is needed because below 4G allocated memory range is # only known after FSP memory init completes. However, FSP migrates to memory -# from cache as ram before it exits FSP Memory Init. Hence we need to add +# from cache as RAM before it exits FSP Memory Init. Hence we need to add # page table entries for this entire range before FSP Memory Init. The # overlapped MMIO ranges will be overridden by below entries. 0xd0000000, 0x100000000, UC, NX # All of MMIO diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index aed2beb..9a61127 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -59,7 +59,7 @@ default 0xe0000000
config FSP_T_ADDR - hex "Intel FSP-T (temp ram init) binary location" + hex "Intel FSP-T (temp RAM init) binary location" depends on ADD_FSP_BINARIES && FSP_CAR default 0xfff30000 help
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39029 )
Change subject: src: capitalize 'RAM' ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39029 )
Change subject: src: capitalize 'RAM' ......................................................................
Patch Set 1:
same questions for the other "capitalization" commits: were there false positives? If not, could you add a lint test to ensure that we don't reintroduce such issues?
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39029 )
Change subject: src: capitalize 'RAM' ......................................................................
src: capitalize 'RAM'
Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/39029 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/cpu/intel/microcode/Kconfig M src/drivers/intel/fsp1_1/exit_car.S M src/drivers/intel/fsp2_0/Kconfig M src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex M src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex M src/mainboard/hp/snb_ivb_laptops/Makefile.inc M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/soc/intel/apollolake/glk_page_map.txt M src/soc/intel/denverton_ns/Kconfig 15 files changed, 21 insertions(+), 21 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index d7d636e..ca72734 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -156,8 +156,8 @@ /* Marker to report base_time. */ { 0, "1st timestamp" }, { TS_START_ROMSTAGE, "start of romstage" }, - { TS_BEFORE_INITRAM, "before ram initialization" }, - { TS_AFTER_INITRAM, "after ram initialization" }, + { TS_BEFORE_INITRAM, "before RAM initialization" }, + { TS_AFTER_INITRAM, "after RAM initialization" }, { TS_END_ROMSTAGE, "end of romstage" }, { TS_START_VBOOT, "start of verified boot" }, { TS_END_VBOOT, "end of verified boot" }, diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index 238aad7..c7bbecb 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -4,4 +4,4 @@ default y help Select this option if you want to update the microcode - during the cache as ram setup. + during the cache as RAM setup. diff --git a/src/drivers/intel/fsp1_1/exit_car.S b/src/drivers/intel/fsp1_1/exit_car.S index 4b2822a..a8db68a 100644 --- a/src/drivers/intel/fsp1_1/exit_car.S +++ b/src/drivers/intel/fsp1_1/exit_car.S @@ -17,7 +17,7 @@ chipset_teardown_car:
pop %ebx - /* Move the stack pointer to real ram */ + /* Move the stack pointer to real RAM */ movl post_car_stack_top, %esp /* Align the stack 16 bytes */ andl $0xfffffff0, %esp diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index a8b3ac4..2d45343 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -61,7 +61,7 @@ and FSP_FD_PATH correctly so FSP splitting works.
config FSP_T_FILE - string "Intel FSP-T (temp ram init) binary path and filename" + string "Intel FSP-T (temp RAM init) binary path and filename" depends on FSP_CAR default "$(obj)/Fsp_T.fd" if FSP_USE_REPO help diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex index 111310a..f3e3e75 100644 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex @@ -15,7 +15,7 @@ # GNU General Public License for more details.
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC -# BAP ODE E20XX has 2GB ram soldered down on the Q7 +# BAP ODE E20XX has 2GB RAM soldered down on the Q7 # Memory setting for DDR-1066
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex index ba3d5ac..6e90bfa 100644 --- a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex @@ -15,7 +15,7 @@ # GNU General Public License for more details.
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC -# BAP ODE E20XX has 2GB ram soldered down on the Q7 +# BAP ODE E20XX has 2GB RAM soldered down on the Q7 # Memory setting for DDR-800
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc index d949ad8..50cea25 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc +++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc @@ -20,5 +20,5 @@ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
-# FIXME: Other variants with same size onboard ram may exist. +# FIXME: Other variants with same size onboard RAM may exist. SPD_SOURCES = hynix_4g diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index d34820e..33abc51 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -133,8 +133,8 @@ { uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 5414120..83157d8 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -99,8 +99,8 @@ { uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 0aa70cd..9fde9f7 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -149,8 +149,8 @@ { uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 6ebd7e0..0784c11 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -58,12 +58,12 @@
top_of_ram = (uintptr_t)cbmem_top(); /* Cache 8MiB below the top of ram. On sandybridge systems the top of - * ram under 4GiB is the start of the TSEG region. It is required to + * RAM under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later * for ramstage before setting up the entire RAM as cacheable. */ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
- /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems + /* Cache 8MiB at the top of ram. Top of RAM on sandybridge systems * is where the TSEG region resides. However, it is not restricted * to SMM mode until SMM has been relocated. By setting the region * to cacheable it provides faster access when relocating the SMM diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 1924ddf..334e6c7 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -144,8 +144,8 @@ { uintptr_t top_of_ram;
- /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. + /* Cache 8 MiB region below the top of RAM and 2 MiB above top of + * RAM to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index dd48d8a..1e871c7 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1636,7 +1636,7 @@ dual_channel_size = MIN(size_ch0, size_ch1) * 2; } else { if (size_ch0 == 0) { - /* ME needs ram on CH0 */ + /* ME needs RAM on CH0 */ size_me = 0; /* TOTEST: bailout? */ } else { diff --git a/src/soc/intel/apollolake/glk_page_map.txt b/src/soc/intel/apollolake/glk_page_map.txt index e96a2db..1a5f11f 100644 --- a/src/soc/intel/apollolake/glk_page_map.txt +++ b/src/soc/intel/apollolake/glk_page_map.txt @@ -1,7 +1,7 @@ 0x00000000, 0x100000000, WB, # RAM # Above entry is needed because below 4G allocated memory range is # only known after FSP memory init completes. However, FSP migrates to memory -# from cache as ram before it exits FSP Memory Init. Hence we need to add +# from cache as RAM before it exits FSP Memory Init. Hence we need to add # page table entries for this entire range before FSP Memory Init. The # overlapped MMIO ranges will be overridden by below entries. 0xd0000000, 0x100000000, UC, NX # All of MMIO diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index aed2beb..9a61127 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -59,7 +59,7 @@ default 0xe0000000
config FSP_T_ADDR - hex "Intel FSP-T (temp ram init) binary location" + hex "Intel FSP-T (temp RAM init) binary location" depends on ADD_FSP_BINARIES && FSP_CAR default 0xfff30000 help