Change in ...coreboot[master]: soc/intel/skylake: Access conf pointer only if its not null
Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30862
Change subject: soc/intel/skylake: Access conf pointer only if its not null ......................................................................
soc/intel/skylake: Access conf pointer only if its not null
conf pointer could be null, access it only if its not null.
Foundby=klocwork BUG=N/A TEST=N/A
Signed-off-by: Pratik Prajapati pratikkumar.v.prajapati@intel.com Change-Id: I0611e15d52edd8e69e4234b8ac602f35efba4015 --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/cpu.c 2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/30862/1
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index c46cfeb..4f49f6e 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -519,7 +519,7 @@ printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
- if (config->eist_enable && config->speed_shift_enable) { + if (config && config->eist_enable && config->speed_shift_enable) { struct cppc_config cppc_config; cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); acpigen_write_CPPC_package(&cppc_config); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0f0518a..cf42372 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. + * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -248,7 +248,7 @@
/* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + if ((msr.lo & (1 << 30)) && conf && conf->tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); /* Bits 27:24 */ msr.lo |= (conf->tcc_offset & 0xf) << 24;
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30862
to look at the new patch set (#2).
Change subject: soc/intel/skylake: Access conf pointer only if its not null ......................................................................
soc/intel/skylake: Access conf pointer only if its not null
conf pointer could be null, access it only if its not null.
Foundby=klocwork BUG=N/A TEST=N/A
Signed-off-by: Pratik Prajapati pratikkumar.v.prajapati@intel.com Change-Id: I0611e15d52edd8e69e4234b8ac602f35efba4015 --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/cpu.c 2 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/30862/2
Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30862 )
Change subject: soc/intel/skylake: Access conf pointer only if its not null ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30862 )
Change subject: soc/intel/skylake: Access conf pointer only if its not null ......................................................................
soc/intel/skylake: Access conf pointer only if its not null
conf pointer could be null, access it only if its not null.
Foundby=klocwork BUG=N/A TEST=N/A
Signed-off-by: Pratik Prajapati pratikkumar.v.prajapati@intel.com Change-Id: I0611e15d52edd8e69e4234b8ac602f35efba4015 Reviewed-on: https://review.coreboot.org/c/30862 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Lijian Zhao lijian.zhao@intel.com --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/cpu.c 2 files changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Lijian Zhao: Looks good to me, approved
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index c46cfeb..f6eb659 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -3,7 +3,7 @@ * * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -519,7 +519,7 @@ printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
- if (config->eist_enable && config->speed_shift_enable) { + if (config && config->eist_enable && config->speed_shift_enable) { struct cppc_config cppc_config; cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); acpigen_write_CPPC_package(&cppc_config); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0f0518a..413fbbb 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. + * Copyright (C) 2015-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -248,7 +248,7 @@
/* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + if ((msr.lo & (1 << 30)) && conf && conf->tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); /* Bits 27:24 */ msr.lo |= (conf->tcc_offset & 0xf) << 24;
-
Lijian Zhao (Code Review) -
Patrick Georgi (Code Review)
-
Pratikkumar V Prajapati (Code Review)