Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86281?usp=email )
Change subject: tree: Use true, false for PcieRpClkReqSupport ......................................................................
tree: Use true, false for PcieRpClkReqSupport
PcieRpClkReqSupport[] is a boolean, so use true/false.
Change-Id: I541ac5361dc0a929459edef7bb1f49c57b137c14 Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/dell/optiplex_3050/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/lenovo/m900_tiny/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb 28 files changed, 79 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/86281/1
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index a5bb944c..e985500 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -90,7 +90,7 @@ device ref pcie_rp3 on # Ethernet controller register "PcieRpEnable[2]" = "true" - register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqSupport[2]" = "true" register "PcieRpClkReqNumber[2]" = "0" register "PcieRpClkSrcNumber[2]" = "0" register "PcieRpAdvancedErrorReporting[2]" = "1" @@ -99,7 +99,7 @@ device ref pcie_rp4 on # Wireless controller register "PcieRpEnable[3]" = "true" - register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqSupport[3]" = "true" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" register "PcieRpAdvancedErrorReporting[3]" = "1" @@ -108,7 +108,7 @@ device ref pcie_rp9 on # NVMe controller register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" register "PcieRpAdvancedErrorReporting[8]" = "1" diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 60136ed..6afde1b 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -254,7 +254,7 @@ register "PcieRpEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "0" register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" end @@ -263,7 +263,7 @@ register "PcieRpEnable[6]" = "true" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpLtrEnable[6]" = "true" - register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqSupport[6]" = "true" register "PcieRpClkReqNumber[6]" = "3" register "PcieRpMaxPayload[6]" = "RpMaxPayload_256" end @@ -272,7 +272,7 @@ register "PcieRpEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "1" register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" end @@ -281,7 +281,7 @@ register "PcieRpEnable[9]" = "true" register "PcieRpAdvancedErrorReporting[9]" = "1" register "PcieRpLtrEnable[9]" = "true" - register "PcieRpClkReqSupport[9]" = "1" + register "PcieRpClkReqSupport[9]" = "true" register "PcieRpClkReqNumber[9]" = "2" register "PcieRpMaxPayload[9]" = "RpMaxPayload_256" # ASPM L0s is broken/unsupported on Qualcomm Atheros QCA6174 (AER: corrected errors) diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index cc36ce8..52cfd3a 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -50,7 +50,7 @@ register "Peg0MaxLinkWidth" = "Peg0_x16"
# Configure PCIe clockgen in PCH - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "0" register "PcieRpClkSrcNumber[0]" = "0" end @@ -114,7 +114,7 @@ device ref pcie_rp1 on end device ref pcie_rp5 on register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[4]" = "true" register "PcieRpClkReqNumber[4]" = "2" register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpLtrEnable[4]" = "true" @@ -125,14 +125,14 @@ register "PcieRpEnable[5]" = "1"
# Disable CLKREQ#, since onboard LAN is always present - register "PcieRpClkReqSupport[5]" = "0" + register "PcieRpClkReqSupport[5]" = "false" register "PcieRpAdvancedErrorReporting[5]" = "1" register "PcieRpLtrEnable[5]" = "true" register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp7 on register "PcieRpEnable[6]" = "1" - register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqSupport[6]" = "false" register "PcieRpClkReqNumber[6]" = "3" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpLtrEnable[6]" = "true" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 15e7064..3976a2e 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -67,7 +67,7 @@ device ref pcie_rp1 on device pci 00.0 on end # x4 TBT register "PcieRpEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" register "PcieRpHotPlug[0]" = "1" @@ -77,7 +77,7 @@ device ref pcie_rp5 on device pci 00.0 on end # x1 LAN register "PcieRpEnable[4]" = "true" - register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[4]" = "true" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" register "PcieRpLtrEnable[4]" = "true" @@ -85,7 +85,7 @@ device ref pcie_rp6 on device pci 00.0 on end # x1 WLAN register "PcieRpEnable[5]" = "true" - register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqSupport[5]" = "true" register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" register "PcieRpLtrEnable[5]" = "true" @@ -94,7 +94,7 @@ device ref pcie_rp9 on device pci 00.0 on end # x4 M.2/M (J_SSD1) register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" register "PcieRpLtrEnable[8]" = "true" diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb index da11085..e95785f 100644 --- a/src/mainboard/dell/optiplex_3050/devicetree.cb +++ b/src/mainboard/dell/optiplex_3050/devicetree.cb @@ -40,7 +40,7 @@ # M.2 SSD device ref pcie_rp21 on register "PcieRpEnable[20]" = "1" - register "PcieRpClkReqSupport[20]" = "1" + register "PcieRpClkReqSupport[20]" = "true" register "PcieRpClkReqNumber[20]" = "3" register "PcieRpAdvancedErrorReporting[20]" = "1" register "PcieRpLtrEnable[20]" = "true" @@ -51,14 +51,14 @@ # Realtek LAN device ref pcie_rp5 on register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "0" + register "PcieRpClkReqSupport[4]" = "false" register "PcieRpHotPlug[4]" = "0" end
# M.2 WiFi device ref pcie_rp8 on register "PcieRpEnable[7]" = "1" - register "PcieRpClkReqSupport[7]" = "0" + register "PcieRpClkReqSupport[7]" = "false" register "PcieRpHotPlug[7]" = "1" end
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index d87db24..ece6081 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -158,7 +158,7 @@ # x1 baseboard WWAN # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard register "PcieRpEnable[2]" = "true" - register "PcieRpClkReqSupport[2]" = "0" + register "PcieRpClkReqSupport[2]" = "false" register "PcieRpMaxPayload[2]" = "RpMaxPayload_256" register "PcieRpLtrEnable[2]" = "true" register "PcieRpAdvancedErrorReporting[2]" = "1" @@ -168,7 +168,7 @@ # x1 baseboard i210 # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard register "PcieRpEnable[5]" = "true" - register "PcieRpClkReqSupport[5]" = "0" + register "PcieRpClkReqSupport[5]" = "false" register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" register "PcieRpLtrEnable[5]" = "true" register "PcieRpAdvancedErrorReporting[5]" = "1" @@ -178,7 +178,7 @@ # x4 FPGA # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "0" + register "PcieRpClkReqSupport[8]" = "false" register "PcieRpHotPlug[8]" = "1" register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" register "PcieRpLtrEnable[8]" = "true" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 5ff4392..f79ad36 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -337,7 +337,7 @@ end # I2C #4 device ref pcie_rp1 on register "PcieRpEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "true" @@ -350,7 +350,7 @@ end device ref pcie_rp5 on register "PcieRpEnable[4]" = "true" - register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[4]" = "true" register "PcieRpClkReqNumber[4]" = "4" register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpLtrEnable[4]" = "true" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index d2bb08e..ed5ecbc 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -290,7 +290,7 @@ # LAN, will be swapped to port 1 by FSP # x1 register "PcieRpEnable[2]" = "true" - register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqSupport[2]" = "true" register "PcieRpClkReqNumber[2]" = "0" register "PcieRpAdvancedErrorReporting[2]" = "1" register "PcieRpLtrEnable[2]" = "true" @@ -305,7 +305,7 @@ device ref pcie_rp4 on # x1 WLAN register "PcieRpEnable[3]" = "true" - register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqSupport[3]" = "true" register "PcieRpClkReqNumber[3]" = "5" register "PcieRpAdvancedErrorReporting[3]" = "1" register "PcieRpLtrEnable[3]" = "true" @@ -318,7 +318,7 @@ device ref pcie_rp5 on # x4 NVMe register "PcieRpEnable[4]" = "true" - register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[4]" = "true" register "PcieRpClkReqNumber[4]" = "1" register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpLtrEnable[4]" = "true" @@ -327,7 +327,7 @@ device ref pcie_rp9 on # 2nd LAN register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "true" @@ -340,7 +340,7 @@ end device ref pcie_rp11 on register "PcieRpEnable[10]" = "true" - register "PcieRpClkReqSupport[10]" = "1" + register "PcieRpClkReqSupport[10]" = "true" register "PcieRpClkReqNumber[10]" = "2" register "PcieRpAdvancedErrorReporting[10]" = "1" register "PcieRpLtrEnable[10]" = "true" @@ -348,7 +348,7 @@ end device ref pcie_rp12 on register "PcieRpEnable[11]" = "true" - register "PcieRpClkReqSupport[11]" = "1" + register "PcieRpClkReqSupport[11]" = "true" register "PcieRpClkReqNumber[11]" = "2" register "PcieRpAdvancedErrorReporting[11]" = "1" register "PcieRpLtrEnable[11]" = "true" diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 7b6de18..697db62 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -117,7 +117,7 @@ device ref pcie_rp7 on # x1 TPU1 register "PcieRpEnable[6]" = "true" - register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqSupport[6]" = "true" register "PcieRpClkReqNumber[6]" = "4" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpLtrEnable[6]" = "true" @@ -126,7 +126,7 @@ device ref pcie_rp8 on # x1 TPU0 register "PcieRpEnable[7]" = "true" - register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqSupport[7]" = "true" register "PcieRpClkReqNumber[7]" = "2" register "PcieRpAdvancedErrorReporting[7]" = "1" register "PcieRpLtrEnable[7]" = "true" @@ -135,7 +135,7 @@ device ref pcie_rp9 on # x4 i350 LAN register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "0" + register "PcieRpClkReqSupport[8]" = "false" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkSrcNumber[8]" = "2" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index bac1ed3..c818060 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -79,7 +79,7 @@ device ref i2c4 on end device ref pcie_rp1 on register "PcieRpEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW0_16" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index d1a3542..922b1525 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -311,7 +311,7 @@ device ref pcie_rp1 on # WLAN register "PcieRpEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 160dfd3..1a64f4a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -324,7 +324,7 @@ device ref i2c4 on end device ref pcie_rp1 on register "PcieRpEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "true" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index e32e5e4..1bb5173 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -367,7 +367,7 @@ device ref pcie_rp4 on # x1 register "PcieRpEnable[3]" = "true" - register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqSupport[3]" = "true" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" register "PcieRpAdvancedErrorReporting[3]" = "1" @@ -380,7 +380,7 @@ device ref pcie_rp5 on # x4 register "PcieRpEnable[4]" = "true" - register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[4]" = "true" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" register "PcieRpAdvancedErrorReporting[4]" = "1" @@ -389,7 +389,7 @@ device ref pcie_rp9 on # x2 register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "2" register "PcieRpAdvancedErrorReporting[8]" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index dfb11ee..0cccd3a 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -362,7 +362,7 @@ end device ref pcie_rp1 on register "PcieRpEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index e64d408..6d3aca8 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -326,7 +326,7 @@ end device ref pcie_rp1 on register "PcieRpEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" @@ -339,7 +339,7 @@ device ref pcie_rp9 on # x2 register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "3" register "PcieRpAdvancedErrorReporting[8]" = "1" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 3251916..737e5a3 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -315,7 +315,7 @@ end device ref pcie_rp1 on register "PcieRpEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 7602bcb..8a89b3a 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -306,7 +306,7 @@ device ref i2c4 on end device ref pcie_rp1 on register "PcieRpEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "true" diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 5da43c2..b784226 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -76,37 +76,37 @@ device ref i2c4 off end device ref pcie_rp6 on register "PcieRpEnable[5]" = "true" - register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqSupport[5]" = "true" register "PcieRpClkReqNumber[5]" = "1" register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp7 on register "PcieRpEnable[6]" = "true" - register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqSupport[6]" = "true" register "PcieRpClkReqNumber[6]" = "2" register "PcieRpClkSrcNumber[6]" = "2" end device ref pcie_rp8 on register "PcieRpEnable[7]" = "true" - register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqSupport[7]" = "true" register "PcieRpClkReqNumber[7]" = "3" register "PcieRpClkSrcNumber[7]" = "3" end device ref pcie_rp9 on register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" end device ref pcie_rp14 on register "PcieRpEnable[13]" = "true" - register "PcieRpClkReqSupport[13]" = "1" + register "PcieRpClkReqSupport[13]" = "true" register "PcieRpClkReqNumber[13]" = "5" register "PcieRpClkSrcNumber[13]" = "5" end device ref pcie_rp17 on register "PcieRpEnable[16]" = "true" - register "PcieRpClkReqSupport[16]" = "1" + register "PcieRpClkReqSupport[16]" = "true" register "PcieRpClkReqNumber[16]" = "7" register "PcieRpClkSrcNumber[16]" = "7" end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 1880cd9..14d5769 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -78,35 +78,35 @@ device ref pcie_rp1 on # PCIE x4 -> SLOT1 register "PcieRpEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "2" register "PcieRpClkSrcNumber[0]" = "2" end device ref pcie_rp5 on # PCIE x1 -> SLOT2/LAN register "PcieRpEnable[4]" = "true" - register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[4]" = "true" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" end device ref pcie_rp6 on # PCIE x1 -> SLOT3 register "PcieRpEnable[5]" = "true" - register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqSupport[5]" = "true" register "PcieRpClkReqNumber[5]" = "1" register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp9 on # PCIE x1 -> WLAN register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" end device ref pcie_rp10 on # PCIE x1 -> WiGig register "PcieRpEnable[9]" = "true" - register "PcieRpClkReqSupport[9]" = "1" + register "PcieRpClkReqSupport[9]" = "true" register "PcieRpClkReqNumber[9]" = "4" register "PcieRpClkSrcNumber[9]" = "4" end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index a030fe7..4d7dd46 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -125,31 +125,31 @@ end device ref pcie_rp3 on register "PcieRpEnable[2]" = "true" - register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqSupport[2]" = "true" register "PcieRpClkReqNumber[2]" = "5" register "PcieRpClkSrcNumber[2]" = "5" end device ref pcie_rp4 on register "PcieRpEnable[3]" = "true" - register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqSupport[3]" = "true" register "PcieRpClkReqNumber[3]" = "2" register "PcieRpClkSrcNumber[3]" = "2" end device ref pcie_rp5 on register "PcieRpEnable[4]" = "true" - register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[4]" = "true" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" end device ref pcie_rp6 on register "PcieRpEnable[5]" = "true" - register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqSupport[5]" = "true" register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkSrcNumber[5]" = "4" end device ref pcie_rp9 on register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "1" register "PcieRpClkSrcNumber[8]" = "1" end diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 1b8e391..789d030 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -149,22 +149,22 @@ device ref pcie_rp3 on end device ref pcie_rp4 on register "PcieRpEnable[3]" = "true" - register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqSupport[3]" = "true" register "PcieRpClkReqNumber[3]" = "2" end device ref pcie_rp5 on register "PcieRpEnable[4]" = "true" - register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[4]" = "true" register "PcieRpClkReqNumber[4]" = "1" end device ref pcie_rp9 on register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "6" end device ref pcie_rp17 on register "PcieRpEnable[16]" = "true" - register "PcieRpClkReqSupport[16]" = "1" + register "PcieRpClkReqSupport[16]" = "true" register "PcieRpClkReqNumber[16]" = "7" end device ref emmc off end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 758b913..fedaf91 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -211,7 +211,7 @@ end device ref pcie_rp1 on register "PcieRpEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "1" chip drivers/wifi/generic register "wake" = "GPE0_DW0_16" @@ -220,7 +220,7 @@ end device ref pcie_rp5 on register "PcieRpEnable[4]" = "true" - register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[4]" = "true" register "PcieRpClkReqNumber[4]" = "2" end device ref uart0 on end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index fd2ae41..ada3e7b 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -187,24 +187,24 @@ device ref pcie_rp1 on end device ref pcie_rp6 on register "PcieRpEnable[5]" = "true" - register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqSupport[5]" = "true" register "PcieRpClkReqNumber[5]" = "0" end device ref pcie_rp8 on # x1 register "PcieRpEnable[7]" = "true" - register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqSupport[7]" = "true" register "PcieRpClkReqNumber[7]" = "3" end device ref pcie_rp9 on # x4 register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "4" end device ref pcie_rp13 on register "PcieRpEnable[12]" = "true" - register "PcieRpClkReqSupport[12]" = "1" + register "PcieRpClkReqSupport[12]" = "true" register "PcieRpClkReqNumber[12]" = "1" end device ref uart0 on end diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb index c2ac2ba..b2bdc6c 100644 --- a/src/mainboard/lenovo/m900_tiny/devicetree.cb +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -162,7 +162,7 @@ end device ref pcie_rp17 on # M.2 2280 / 2242 - SSD register "PcieRpEnable[16]" = "1" - register "PcieRpClkReqSupport[16]" = "1" + register "PcieRpClkReqSupport[16]" = "true" register "PcieRpClkReqNumber[16]" = "1" register "PcieRpAdvancedErrorReporting[16]" = "1" register "PcieRpLtrEnable[16]" = "true" @@ -171,7 +171,7 @@ end device ref pcie_rp7 on # M.2 2230 - WLAN register "PcieRpEnable[6]" = "1" - register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqSupport[6]" = "true" register "PcieRpClkReqNumber[6]" = "11" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpLtrEnable[6]" = "true" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 30152b5..1da9ac5 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -188,7 +188,7 @@ register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkSrcNumber[8]" = "5" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "0" smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" diff --git a/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb index 8a2bf28..37be8cd 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb @@ -24,7 +24,7 @@ end device ref pcie_rp5 on end device ref pcie_rp9 on - register "PcieRpClkReqSupport[8]" = "0" + register "PcieRpClkReqSupport[8]" = "false" register "PcieRpClkReqNumber[8]" = "2" end end diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index ed61df8..63e337d 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -85,7 +85,7 @@ device ref uart2 on end device ref pcie_rp6 on register "PcieRpEnable[5]" = "1" - register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqSupport[5]" = "true" register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkSrcNumber[5]" = "4" register "PcieRpLtrEnable[5]" = "true" @@ -97,7 +97,7 @@ end device ref pcie_rp9 on register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "0" register "PcieRpClkSrcNumber[8]" = "0" register "PcieRpLtrEnable[8]" = "true" diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 10a5750..273bae5 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -134,7 +134,7 @@ device ref pcie_rp1 on # Root port #1 x4 (TBT) register "PcieRpEnable[0]" = "true" - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[0]" = "true" register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" register "PcieRpAdvancedErrorReporting[0]" = "1" @@ -144,7 +144,7 @@ device ref pcie_rp5 on # Root port #5 x1 (LAN) register "PcieRpEnable[4]" = "true" - register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[4]" = "true" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" register "PcieRpAdvancedErrorReporting[4]" = "1" @@ -153,7 +153,7 @@ device ref pcie_rp6 on # Root port #6 x1 (WLAN) register "PcieRpEnable[5]" = "true" - register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqSupport[5]" = "true" register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" register "PcieRpAdvancedErrorReporting[5]" = "1" @@ -162,7 +162,7 @@ device ref pcie_rp9 on # Root port #9 x4 (NVMe) register "PcieRpEnable[8]" = "true" - register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqSupport[8]" = "true" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" register "PcieRpAdvancedErrorReporting[8]" = "1"
-
Elyes Haouas (Code Review)