[XS] Change in coreboot[main]: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume"

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Subrata Banik.

Karthik Ramasubramanian has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86111?usp=email )

Change subject: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume"
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Patch Set 4:

(1 comment)

File src/soc/intel/alderlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/86111/comment/91965b7e_47c7adab?usp... :
PS4, Line 202: ps->prev_sleep_state == ACPI_S5
> We are only issuing a warm reset post UFS disablement in the S5 flow. […]

When the isssue happens, the previous sleep state is read as S0. We have always asssociated this with warm reset.

But CSE FW status register does not indicate warm reset. CSE FW status register reads as  `ME: HFSTS2                      : 0x3B850106`. Bits 24 - 27 (0xB) indicate the reset type as `Power cycle reset through CMoff`. If it were warm reset, bits 24 - 27 would read as 0x9.

So in addition to S5 reset, if we also trigger a warm reset for any other non warm reset as indicated in CSE FW status register, that will simplify the solution for this issue a lot.