Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45796 )
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
soc/intel: Make use of PMC low power program from common block
List of changes: 1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory 2. Remove redundant PMC programming from SoC and refer to common code block 3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC function.
Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/finalize.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/finalize.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/finalize.c 12 files changed, 34 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45796/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f792e70..ae18f94 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -97,6 +97,7 @@ select PLATFORM_USES_FSP2_0 select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 315c67a..9eb9cbe 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -44,7 +45,6 @@ uint32_t reg32; uint8_t *pmcbase; config_t *config; - uint8_t reg8;
tco_lockdown();
@@ -70,17 +70,12 @@ */ config = config_of_soc(); pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer();
if (config->s0ix_enable) { /* Disable XTAL shutdown qualification for low power idle. */ - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); + pmc_ignore_xtal_shutdown();
if (config->cppmvric2_adsposcdis) { /* Enable Audio DSP OSC qualification for S0ix */ diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index ba04a4f..1a33c92 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -33,6 +33,7 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index e9b3f21..bae8bcf 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <soc/p2sb.h> @@ -22,10 +23,7 @@
static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8;
/* TCO Lock down */ tco_lockdown(); @@ -44,19 +42,12 @@ * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer();
/* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown();
pmc_clear_pmcon_sts(); } diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 60cb5e5..3869c95 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -31,6 +31,7 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 53e3cba..363f579 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -40,10 +41,7 @@
static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8;
/* TCO Lock down */ tco_lockdown(); @@ -69,19 +67,12 @@ * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer();
/* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown();
pch_handle_sideband(config);
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 2282655..9ebf3b7 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -33,6 +33,7 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 08a6bab..ef574d9 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -40,10 +41,7 @@
static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8;
/* TCO Lock down */ tco_lockdown(); @@ -62,19 +60,12 @@ * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer();
/* Disable XTAL shutdown qualification for low power idle. */ if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + pmc_ignore_xtal_shutdown();
pch_handle_sideband(config);
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 155df58..c48b902 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -43,6 +43,7 @@ select REG_SCRIPT select SA_ENABLE_DPR select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 0294a72..ff32189 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -13,6 +13,7 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -44,17 +45,13 @@
static void pch_finalize_script(struct device *dev) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - u8 reg8;
tco_lockdown();
/* Display me status before we hide it */ intel_me_status();
- pmcbase = pmc_mmio_regs(); config = config_of(dev);
/* @@ -73,18 +70,12 @@ * Disabling ACPI PM timer also switches off TCO */
- if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer();
/* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown();
/* we should disable Heci1 based on the devicetree policy */ if (config->HeciEnabled == 0) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 7e143c1..7db43ca 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -34,6 +34,7 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 5bf01de..2cc9671 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -15,6 +15,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -28,10 +29,7 @@
static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8;
/* TCO Lock down */ tco_lockdown(); @@ -50,19 +48,12 @@ * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer();
/* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown();
pmc_clear_pmcon_sts(); }
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45796
to look at the new patch set (#3).
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
soc/intel: Make use of PMC low power program from common block
List of changes: 1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory 2. Remove redundant PMC programming from SoC and refer to common code block 3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC function.
Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/finalize.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/finalize.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/finalize.c 12 files changed, 35 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45796/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45796 )
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
Patch Set 3: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45796 )
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45796/3/src/soc/intel/cannonlake/fi... File src/soc/intel/cannonlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/45796/3/src/soc/intel/cannonlake/fi... PS3, Line 43: static void pch_finalize(void) These functions are still rather similar between SoCs.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45796 )
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45796/3/src/soc/intel/cannonlake/fi... File src/soc/intel/cannonlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/45796/3/src/soc/intel/cannonlake/fi... PS3, Line 43: static void pch_finalize(void)
These functions are still rather similar between SoCs.
Yes Angel, only because of CNL platform, right now i'm unable to move this code into common, bt will address this during common code phase 2.0 that we are planning before EOY.
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45796
to look at the new patch set (#4).
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
soc/intel: Make use of PMC low power program from common block
List of changes: 1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory 2. Remove redundant PMC programming from SoC and refer to common code block 3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC function.
Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/include/soc/pmc.h M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/elkhartlake/include/soc/pmc.h M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/include/soc/pmc.h M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/finalize.c M src/soc/intel/jasperlake/include/soc/pmc.h M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/include/soc/pmc.h M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/finalize.c M src/soc/intel/tigerlake/include/soc/pmc.h 18 files changed, 41 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45796/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45796 )
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45796/3/src/soc/intel/cannonlake/fi... File src/soc/intel/cannonlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/45796/3/src/soc/intel/cannonlake/fi... PS3, Line 43: static void pch_finalize(void)
Yes Angel, only because of CNL platform, right now i'm unable to move this code into common, bt will […]
Alright. CNL (Cannon Lake, the 10nm one) is not very popular: the i3-8121U [1] is the only CNL part that was released. And since there's no FSP for Cannon Lake in the public Intel FSP repo [2], we might as well drop support for CNL in coreboot.
Skylake is also different in some ways, but we can still take care of it.
[1]: https://ark.intel.com/content/www/us/en/ark/products/136863/intel-core-i3-81... [2]: https://github.com/intel/FSP
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45796 )
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45796/3/src/soc/intel/cannonlake/fi... File src/soc/intel/cannonlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/45796/3/src/soc/intel/cannonlake/fi... PS3, Line 43: static void pch_finalize(void)
Alright. […]
Sounds like plan. Thanks Angel 👍
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45796 )
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45796/3/src/soc/intel/cannonlake/fi... File src/soc/intel/cannonlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/45796/3/src/soc/intel/cannonlake/fi... PS3, Line 43: static void pch_finalize(void)
Sounds like plan. […]
We used all of this "cannonlake" code actually supports whiskey lake, coffee lake, and comet lake as well. There are 9 mainboard families in coreboot that use this cannonlake code (`git grep soc/intel/cannonlake -- src/*.cb | cut -d'/' -f'1,2,3,4' | sort | uniq | wc -l`)
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45796 )
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45796/3/src/soc/intel/cannonlake/fi... File src/soc/intel/cannonlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/45796/3/src/soc/intel/cannonlake/fi... PS3, Line 43: static void pch_finalize(void)
We used all of this "cannonlake" code actually supports whiskey lake, coffee lake, and comet lake as […]
Yes, looking at https://review.coreboot.org/c/coreboot/+/37604 it appears to be CML changes rather CNL hence might be required and this register is not common for all chipset hence not a good idea to move into pmclib 😞
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45796 )
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
Patch Set 6:
Angel/Furquan/Tim: request you to review this CL
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45796 )
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
Patch Set 6: Code-Review+2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45796 )
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
Patch Set 6:
Patch Set 6:
Angel/Furquan/Tim: request you to review this CL
Thanks Angel
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45796 )
Change subject: soc/intel: Make use of PMC low power program from common block ......................................................................
soc/intel: Make use of PMC low power program from common block
List of changes: 1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory 2. Remove redundant PMC programming from SoC and refer to common code block 3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC function.
Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45796 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/include/soc/pmc.h M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/elkhartlake/include/soc/pmc.h M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/include/soc/pmc.h M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/finalize.c M src/soc/intel/jasperlake/include/soc/pmc.h M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/include/soc/pmc.h M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/finalize.c M src/soc/intel/tigerlake/include/soc/pmc.h 18 files changed, 41 insertions(+), 79 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index b0335cf..9bd9f43 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -96,6 +96,7 @@ select PLATFORM_USES_FSP2_0 select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 315c67a..9eb9cbe 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -44,7 +45,6 @@ uint32_t reg32; uint8_t *pmcbase; config_t *config; - uint8_t reg8;
tco_lockdown();
@@ -70,17 +70,12 @@ */ config = config_of_soc(); pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer();
if (config->s0ix_enable) { /* Disable XTAL shutdown qualification for low power idle. */ - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); + pmc_ignore_xtal_shutdown();
if (config->cppmvric2_adsposcdis) { /* Enable Audio DSP OSC qualification for S0ix */ diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 2c2db03..3576d80 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -98,6 +98,7 @@ #define PCH2CPU_TT_EN (1 << 26)
#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 1a0bfd2..7e78805 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -32,6 +32,7 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index e9b3f21..bae8bcf 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <soc/p2sb.h> @@ -22,10 +23,7 @@
static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8;
/* TCO Lock down */ tco_lockdown(); @@ -44,19 +42,12 @@ * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer();
/* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown();
pmc_clear_pmcon_sts(); } diff --git a/src/soc/intel/elkhartlake/include/soc/pmc.h b/src/soc/intel/elkhartlake/include/soc/pmc.h index 9e6d22f..f331961 100644 --- a/src/soc/intel/elkhartlake/include/soc/pmc.h +++ b/src/soc/intel/elkhartlake/include/soc/pmc.h @@ -98,6 +98,7 @@ #define PCH2CPU_TT_EN (1 << 26)
#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index cad3119..0343263 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -30,6 +30,7 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 53e3cba..363f579 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -40,10 +41,7 @@
static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8;
/* TCO Lock down */ tco_lockdown(); @@ -69,19 +67,12 @@ * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer();
/* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown();
pch_handle_sideband(config);
diff --git a/src/soc/intel/icelake/include/soc/pmc.h b/src/soc/intel/icelake/include/soc/pmc.h index 961207c..26dae7e 100644 --- a/src/soc/intel/icelake/include/soc/pmc.h +++ b/src/soc/intel/icelake/include/soc/pmc.h @@ -98,6 +98,7 @@ #define PCH2CPU_TT_EN (1 << 26)
#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 53d6e64..2da4284 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -32,6 +32,7 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 08a6bab..1badad3 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -40,10 +41,7 @@
static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8;
/* TCO Lock down */ tco_lockdown(); @@ -62,19 +60,12 @@ * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer();
/* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown();
pch_handle_sideband(config);
diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index 9eaa812..34172f8 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -98,6 +98,7 @@ #define PCH2CPU_TT_EN (1 << 26)
#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 6bdb615..c6e3a22 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -42,6 +42,7 @@ select REG_SCRIPT select SA_ENABLE_DPR select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 0294a72..ff32189 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -13,6 +13,7 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -44,17 +45,13 @@
static void pch_finalize_script(struct device *dev) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - u8 reg8;
tco_lockdown();
/* Display me status before we hide it */ intel_me_status();
- pmcbase = pmc_mmio_regs(); config = config_of(dev);
/* @@ -73,18 +70,12 @@ * Disabling ACPI PM timer also switches off TCO */
- if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer();
/* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown();
/* we should disable Heci1 based on the devicetree policy */ if (config->HeciEnabled == 0) diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 6d52b9d..350649a 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -78,6 +78,7 @@ #define PMSYNC_TPR_CFG 0xc4 #define PMSYNC_LOCK (1 << 31) #define PCH_PWRM_ACPI_TMR_CTL 0xfc +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x120 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index ac98779..bf05d37 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -33,6 +33,7 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 5bf01de..2cc9671 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -15,6 +15,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -28,10 +29,7 @@
static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8;
/* TCO Lock down */ tco_lockdown(); @@ -50,19 +48,12 @@ * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer();
/* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown();
pmc_clear_pmcon_sts(); } diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index b7a97cc8..f926799 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -126,6 +126,7 @@ enum pch_pmc_xtal pmc_get_xtal_freq(void);
#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x))