Change in coreboot[master]: soraka: move WLAN_PE_RST gpio pad entry to early_gpio_table

[Divya Chellappa (Code Review)]

Divya Chellappa has uploaded this change for review. ( https://review.coreboot.org/22587

Change subject: soraka: move WLAN_PE_RST gpio pad entry to early_gpio_table
......................................................................

soraka: move WLAN_PE_RST gpio pad entry to early_gpio_table

RSMRST reset config doesn't preserve the gpio configuration
across deepSx, in such scenarios, gpio pad configuration
should be done in early pad configuration in bootblock.

BUG=none
BRANCH=none
TEST= WiFi functionality across S3, DeepS3, S0ix and warm/cold reboot.

Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6
Signed-off-by: Divya Chellap 
---
M src/mainboard/google/poppy/variants/soraka/gpio.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/22587/1

diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c
index 84a8294..ae1d07d 100644
--- a/src/mainboard/google/poppy/variants/soraka/gpio.c
+++ b/src/mainboard/google/poppy/variants/soraka/gpio.c
@@ -78,8 +78,7 @@
    PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
    /* B7  : SRCCLKREQ2# ==> NC */
    PAD_CFG_NC(GPP_B7),
-	/* B8  : SRCCLKREQ3# ==> WLAN_PE_RST */
-	PAD_CFG_GPO(GPP_B8, 0, RSMRST),
+
    /* B9  : SRCCLKREQ4# ==> NC */
    PAD_CFG_NC(GPP_B9),
    /* B10 : SRCCLKREQ5# ==> NC */
@@ -371,6 +370,8 @@

/* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
+	/* B8  : SRCCLKREQ3# ==> WLAN_PE_RST */
+	PAD_CFG_GPO(GPP_B8, 0, RSMRST),
 #if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
    /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
    PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
@@ -388,7 +389,6 @@
    /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
    PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 #endif
-
    /* Ensure UART pins are in native mode for H1. */
    /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
    PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),