Zheng Bao (zheng.bao@amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11749
-gerrit
commit b364122f6cd940ba4e925f455d17bc5ae331a68a Author: Zheng Bao fishbaozi@gmail.com Date: Fri Nov 13 00:41:45 2015 +0800
AMD/bettong: Add UART support
The function delay in uart8250mem.c is not enough for hudson. Need a seprate patch to fix that.
Select HUDSON_UART to enable this feature.
The UART is test at BIOS stage.
Since it is not a standart UART device, the windows internal UART driver doesnt support it. I guess we need a driver to use it on windows.
Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb Signed-off-by: Zheng Bao zheng.bao@amd.com Signed-off-by: Zheng Bao fishbaozi@gmail.com --- src/southbridge/amd/agesa/hudson/acpi/uart.asl | 82 ++++++++++++++++++++++++++ src/southbridge/amd/pi/hudson/Kconfig | 16 +++++ src/southbridge/amd/pi/hudson/Makefile.inc | 5 ++ src/southbridge/amd/pi/hudson/early_setup.c | 29 +++++++++ src/southbridge/amd/pi/hudson/uart.c | 26 ++++++++ 5 files changed, 158 insertions(+)
diff --git a/src/southbridge/amd/agesa/hudson/acpi/uart.asl b/src/southbridge/amd/agesa/hudson/acpi/uart.asl new file mode 100644 index 0000000..dcaab22 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/acpi/uart.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + Scope(_SB.FUR0) + { + Device(UART) + { + Name(_HID, "UTK0001") + Name(_CID, "UARTTest") + Name(_UID, Zero) + Method(_CRS, 0, NotSerialized) + { + Name(RBUF, Buffer(0x22) + { + 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35, + 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00, + 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F, + 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x30, 0x00, + 0x79, 0x00 + }) + Return(RBUF) + } + Method(_STA, 0, NotSerialized) + { + If(LEqual(MWTT, Zero)) + { + Return(0x0F) + } + Else + { + Return(Zero) + } + } + } + } +/* + Scope(_SB.FUR1) + { + Device(UART) + { + Name(_HID, "UTK0001") + Name(_CID, "UARTTest") + Name(_UID, One) + Method(_CRS, 0, NotSerialized) + { + Name(RBUF, Buffer(0x22) + { + 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35, + 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00, + 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F, + 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x31, 0x00, + 0x79, 0x00 + }) + Return(RBUF) + } + Method(_STA, 0, NotSerialized) + { + If(LEqual(MWTT, Zero)) + { + Return(0x0F) + } + Else + { + Return(Zero) + } + } + } + } +*/ diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c720791..94a313d 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -227,3 +227,19 @@ config AZ_PIN bit 5,4 - pin 2 bit 7,6 - pin 3 endif + +config HUDSON_UART + bool "UART controller on Kern." + default n + depends on SOUTHBRIDGE_AMD_PI_KERN + select DRIVERS_UART_8250MEM + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + help + There are two UART controllers in Kern. + The UART registers are memory-mapped. UART + controller 0 registers range from FEDC_6000h + to FEDC_6FFFh. UART controller 1 registers + range from FEDC_8000h to FEDC_8FFFh. + + diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 00d150f..08c2b39 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -50,6 +50,11 @@ romstage-y += imc.c ramstage-y += imc.c endif
+ifeq ($(CONFIG_HUDSON_UART), y) +romstage-y += uart.c +ramstage-y += uart.c +endif + smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 14ffd8b..9ba8fa8 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -18,14 +18,41 @@
#include <stdint.h> #include <arch/io.h> +#include <cpu/x86/msr.h> #include <arch/acpi.h> #include <console/console.h> #include <reset.h> #include <arch/cpu.h> +#include <delay.h> #include <cbmem.h> +#include <Fch/Fch.h> #include "hudson.h" #include "pci_devs.h"
+static void configure_hudson_uart(void) +{ +#if CONFIG_HUDSON_UART + msr_t msr; + u8 byte; + + msr = rdmsr(0x1B); + msr.lo |= 1 << 11; + wrmsr(0x1B, msr); + byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2); + byte |= 1 << 3; + write8((void *)ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2, byte); + byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + 0x62); + byte |= 1 << 3; + write8((void *)ACPI_MMIO_BASE + AOAC_BASE + 0x62, byte); + write8((void *)ACPI_MMIO_BASE + 0xD00 + 0x89, 0); + write8((void *)ACPI_MMIO_BASE + 0xD00 + 0x8A, 0); + write8((void *)ACPI_MMIO_BASE + 0xD00 + 0x8E, 0); + write8((void *)ACPI_MMIO_BASE + 0xD00 + 0x8F, 0); + + udelay(2000); + write8((void *)0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88, 0x01); /* reset UART */ +#endif +} void hudson_pci_port80(void) { u8 byte; @@ -69,6 +96,8 @@ void hudson_pci_port80(void) byte = pci_read_config8(dev, 0x4A); byte &= ~(1 << 5); /* disable lpc port 80 */ pci_write_config8(dev, 0x4A, byte); + + configure_hudson_uart(); }
void hudson_lpc_port80(void) diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c new file mode 100644 index 0000000..5d88204 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/uart.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> + +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1)); +} + +unsigned int uart_platform_refclk(void) +{ + return 48000000; +}
-
Zheng Bao