Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
mb/emulation/qemu-q35: Account for TSEG
TSEG is located below TOLUD. The size is configured in ESMRAMC but can also be configured with "-global mch.extended-tseg-mbytes=5" command line argument. Note that the size in ESMRAMC needs to be 'invalid' for this to take action.
Coreboot will leave TSEG at the default 1MiB.
Change-Id: I5fd82a42d6602f1369bb3c69556c46f537542705 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/memmap.c 3 files changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/48236/1
diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index b30b381..3fd37c3 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -4,6 +4,7 @@ #include <arch/io.h> #include <arch/romstage.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include "memory.h" #include "fw_cfg.h"
@@ -40,6 +41,8 @@ return tomk; }
+#include <device/pci_ops.h> + void *cbmem_top_chipset(void) { uintptr_t top = 0; @@ -50,6 +53,14 @@ top = (uintptr_t)qemu_get_memory_size() * 1024; }
+ /* With CONFIG(SMM_TSEG) we will lock down TSEG so cbmem needs to be lower. */ + if (CONFIG(BOARD_EMULATION_QEMU_X86_Q35) && CONFIG(SMM_TSEG)) { + uintptr_t smm_base; + uintptr_t smm_size; + smm_region(&smm_base, &smm_size); + top = smm_base; + } + return (void *)top; }
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index ddcf6da..4bd91f0 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -2,17 +2,21 @@
romstage-y += ../qemu-i440fx/fw_cfg.c romstage-y += ../qemu-i440fx/memmap.c +romstage-y += memmap.c
postcar-y += ../qemu-i440fx/fw_cfg.c postcar-y += ../qemu-i440fx/memmap.c postcar-y += ../qemu-i440fx/exit_car.S +postcar-y += memmap.c
ramstage-y += ../qemu-i440fx/fw_cfg.c ramstage-y += ../qemu-i440fx/memmap.c ramstage-y += ../qemu-i440fx/northbridge.c +ramstage-y += memmap.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += memmap.c diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c new file mode 100644 index 0000000..5171ee4 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <cpu/x86/smm.h> +#include <device/pci_ops.h> +#include <mainboard/emulation/qemu-i440fx/memory.h> +#include <mainboard/emulation/qemu-i440fx/fw_cfg.h> + +#define EXT_TSEG_MBYTES 0x50 + +#define SMRAMC 0x9d +#define G_SMRAME (1 << 3) +#define D_LCK (1 << 4) +#define D_CLS (1 << 5) +#define D_OPEN (1 << 6) +#define ESMRAMC 0x9e +#define T_EN (1 << 0) +#define TSEG_SZ_MASK (3 << 1) +#define H_SMRAME (1 << 7) + +void smm_region(uintptr_t *start, size_t *size) +{ + uint8_t esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + + switch ((esmramc & TSEG_SZ_MASK) >> 1) + { + case 0: + *size = 1 * MiB; + break; + case 1: + *size = 2 * MiB; + break; + case 2: + *size = 8 * MiB; + break; + default: + *size = pci_read_config16(PCI_DEV(0, 0, 0), EXT_TSEG_MBYTES) * MiB; + } + + *start = qemu_get_memory_size() * KiB - *size; + printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %ld MiB\n", smm_base, smm_size / MiB); + +} +
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48236
to look at the new patch set (#3).
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
mb/emulation/qemu-q35: Account for TSEG
TSEG is located below TOLUD. The size is configured in ESMRAMC but can also be configured with "-global mch.extended-tseg-mbytes=5" command line argument. Note that the size in ESMRAMC needs to be 'invalid' for this to take action.
Coreboot will leave TSEG at the default 1MiB.
Change-Id: I5fd82a42d6602f1369bb3c69556c46f537542705 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/memmap.c 3 files changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/48236/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48236/3/src/mainboard/emulation/qem... File src/mainboard/emulation/qemu-q35/memmap.c:
https://review.coreboot.org/c/coreboot/+/48236/3/src/mainboard/emulation/qem... PS3, Line 26: switch ((esmramc & TSEG_SZ_MASK) >> 1) that open brace { should be on the previous line
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48236
to look at the new patch set (#4).
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
mb/emulation/qemu-q35: Account for TSEG
TSEG is located below TOLUD. The size is configured in ESMRAMC but can also be configured with "-global mch.extended-tseg-mbytes=5" command line argument. Note that the size in ESMRAMC needs to be 'invalid' for this to take action.
coreboot will leave TSEG at the default 1MiB.
Change-Id: I5fd82a42d6602f1369bb3c69556c46f537542705 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/memmap.c 3 files changed, 55 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/48236/4
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48236
to look at the new patch set (#6).
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
mb/emulation/qemu-q35: Account for TSEG
TSEG is located below TOLUD. The size is configured in ESMRAMC but can also be configured with "-global mch.extended-tseg-mbytes=5" command line argument. Note that the size in ESMRAMC needs to be 'invalid' for this to take action.
coreboot will leave TSEG at the default 1MiB.
Change-Id: I5fd82a42d6602f1369bb3c69556c46f537542705 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/memmap.c 3 files changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/48236/6
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48236
to look at the new patch set (#7).
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
mb/emulation/qemu-q35: Account for TSEG
TSEG is located below TOLUD. The size is configured in ESMRAMC but can also be configured with "-global mch.extended-tseg-mbytes=5" command line argument. Note that the size in ESMRAMC needs to be 'invalid' (3) for this to take action.
coreboot will leave TSEG at the default 1MiB.
Note that even if TSEG does not end up being used, it is likely a good idea to not put anything there as if SMM gets locked down by something else it will suddenly be inaccessible.
Change-Id: I5fd82a42d6602f1369bb3c69556c46f537542705 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/memmap.c 3 files changed, 55 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/48236/7
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48236/7/src/mainboard/emulation/qem... File src/mainboard/emulation/qemu-q35/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48236/7/src/mainboard/emulation/qem... PS7, Line 10: postcar-y += memmap.c Are this and the later entries needed? I thought since we pass the top pointer from stage to stage now, we only call cbmem_top_chipset() in romstage. Or is this just in preparation?
https://review.coreboot.org/c/coreboot/+/48236/7/src/mainboard/emulation/qem... File src/mainboard/emulation/qemu-q35/memmap.c:
https://review.coreboot.org/c/coreboot/+/48236/7/src/mainboard/emulation/qem... PS7, Line 42: ld %zu
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48236/7/src/mainboard/emulation/qem... File src/mainboard/emulation/qemu-q35/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48236/7/src/mainboard/emulation/qem... PS7, Line 10: postcar-y += memmap.c
Are this and the later entries needed? I thought since we pass the top pointer from stage to stage now, we only call cbmem_top_chipset() in romstage. Or is this just in preparation?
Oh right, it's not strictly needed now. I can move postcar/ramstage linking to later patches.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48236/7/src/mainboard/emulation/qem... File src/mainboard/emulation/qemu-q35/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/48236/7/src/mainboard/emulation/qem... PS7, Line 10: postcar-y += memmap.c
Are this and the later entries needed? I thought since we pass the top […]
If it's going to be needed, probably not worth the hassle. Your call.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 7: Code-Review+2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48236
to look at the new patch set (#8).
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
mb/emulation/qemu-q35: Account for TSEG
TSEG is located below TOLUD. The size is configured in ESMRAMC but can also be configured with "-global mch.extended-tseg-mbytes=5" command line argument. Note that the size in ESMRAMC needs to be 'invalid' (3) for this to take action.
coreboot will leave TSEG at the default 1MiB.
Note that even if TSEG does not end up being used, it is likely a good idea to not put anything there as if SMM gets locked down by something else it will suddenly be inaccessible.
Change-Id: I5fd82a42d6602f1369bb3c69556c46f537542705 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/memmap.c 3 files changed, 55 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/48236/8
Attention is currently required from: Nico Huber. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/emulation/qemu-q35/memmap.c:
https://review.coreboot.org/c/coreboot/+/48236/comment/fe7272bb_d9478a9b PS7, Line 42: ld
%zu
Done
Attention is currently required from: Nico Huber, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 8: Code-Review+1
(4 comments)
File src/mainboard/emulation/qemu-i440fx/memmap.c:
https://review.coreboot.org/c/coreboot/+/48236/comment/091cd64e_24626424 PS8, Line 56: uintptr_t size_t
https://review.coreboot.org/c/coreboot/+/48236/comment/bf9acc97_2fbeaf35 PS8, Line 57: smm_base top ?
File src/mainboard/emulation/qemu-q35/memmap.c:
https://review.coreboot.org/c/coreboot/+/48236/comment/8e4d0bdd_75a00636 PS8, Line 25: esmramc Should we check the enable bit?
https://review.coreboot.org/c/coreboot/+/48236/comment/d8d9e93a_7c09a1aa PS8, Line 42: 0x%08lx %p ?
Attention is currently required from: Nico Huber, Arthur Heymans. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48236
to look at the new patch set (#9).
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
mb/emulation/qemu-q35: Account for TSEG
TSEG is located below TOLUD. The size is configured in ESMRAMC but can also be configured with "-global mch.extended-tseg-mbytes=5" command line argument. Note that the size in ESMRAMC needs to be 'invalid' (3) for this to take action.
coreboot will leave TSEG at the default 1MiB.
Note that even if TSEG does not end up being used, it is likely a good idea to not put anything there as if SMM gets locked down by something else it will suddenly be inaccessible.
Change-Id: I5fd82a42d6602f1369bb3c69556c46f537542705 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/memmap.c 3 files changed, 53 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/48236/9
Attention is currently required from: Nico Huber, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 8:
(4 comments)
File src/mainboard/emulation/qemu-i440fx/memmap.c:
https://review.coreboot.org/c/coreboot/+/48236/comment/5f1ce8a8_f1d37f5a PS8, Line 56: uintptr_t
size_t
Done
https://review.coreboot.org/c/coreboot/+/48236/comment/a3cdccc8_dc01f5d6 PS8, Line 57: smm_base
top ?
Done
File src/mainboard/emulation/qemu-q35/memmap.c:
https://review.coreboot.org/c/coreboot/+/48236/comment/a3b35352_761a691f PS8, Line 25: esmramc
Should we check the enable bit?
The lock + enable bits are only set at the end of SMM relocation in the follow up patch. So TSEG needs to be accounted for early on.
https://review.coreboot.org/c/coreboot/+/48236/comment/3b6c5226_50a2e1a8 PS8, Line 42: 0x%08lx
%p ?
that's for void *. *start is of type uintptr_t
Attention is currently required from: Nico Huber, Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/emulation/qemu-i440fx/memmap.c:
https://review.coreboot.org/c/coreboot/+/48236/comment/f5a06e33_792a65d6 PS9, Line 55: size_t smm_size; code indent should use tabs where possible
Attention is currently required from: Nico Huber, Angel Pons. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48236
to look at the new patch set (#10).
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
mb/emulation/qemu-q35: Account for TSEG
TSEG is located below TOLUD. The size is configured in ESMRAMC but can also be configured with "-global mch.extended-tseg-mbytes=5" command line argument. Note that the size in ESMRAMC needs to be 'invalid' (3) for this to take action.
coreboot will leave TSEG at the default 1MiB.
Note that even if TSEG does not end up being used, it is likely a good idea to not put anything there as if SMM gets locked down by something else it will suddenly be inaccessible.
Change-Id: I5fd82a42d6602f1369bb3c69556c46f537542705 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/memmap.c 3 files changed, 53 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/48236/10
Attention is currently required from: Nico Huber, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 10:
(2 comments)
File src/mainboard/emulation/qemu-q35/memmap.c:
https://review.coreboot.org/c/coreboot/+/48236/comment/7abbb257_c22134f4 PS8, Line 25: esmramc
Should we check the enable bit? […]
Ack
https://review.coreboot.org/c/coreboot/+/48236/comment/bf7527e5_b40bf82f PS8, Line 42: 0x%08lx
%p ? […]
Ack
Attention is currently required from: Nico Huber, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 10: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
mb/emulation/qemu-q35: Account for TSEG
TSEG is located below TOLUD. The size is configured in ESMRAMC but can also be configured with "-global mch.extended-tseg-mbytes=5" command line argument. Note that the size in ESMRAMC needs to be 'invalid' (3) for this to take action.
coreboot will leave TSEG at the default 1MiB.
Note that even if TSEG does not end up being used, it is likely a good idea to not put anything there as if SMM gets locked down by something else it will suddenly be inaccessible.
Change-Id: I5fd82a42d6602f1369bb3c69556c46f537542705 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/48236 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/memmap.c 3 files changed, 53 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index b30b381..75ab352 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -4,6 +4,7 @@ #include <arch/io.h> #include <arch/romstage.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include "memory.h" #include "fw_cfg.h"
@@ -50,6 +51,11 @@ top = (uintptr_t)qemu_get_memory_size() * 1024; }
+ if (CONFIG(BOARD_EMULATION_QEMU_X86_Q35)) { + size_t smm_size; + smm_region(&top, &smm_size); + } + return (void *)top; }
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index ddcf6da..4bd91f0 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -2,17 +2,21 @@
romstage-y += ../qemu-i440fx/fw_cfg.c romstage-y += ../qemu-i440fx/memmap.c +romstage-y += memmap.c
postcar-y += ../qemu-i440fx/fw_cfg.c postcar-y += ../qemu-i440fx/memmap.c postcar-y += ../qemu-i440fx/exit_car.S +postcar-y += memmap.c
ramstage-y += ../qemu-i440fx/fw_cfg.c ramstage-y += ../qemu-i440fx/memmap.c ramstage-y += ../qemu-i440fx/northbridge.c +ramstage-y += memmap.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += memmap.c diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c new file mode 100644 index 0000000..a8b1433 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <device/pci_ops.h> +#include <mainboard/emulation/qemu-i440fx/memory.h> +#include <mainboard/emulation/qemu-i440fx/fw_cfg.h> + +#define EXT_TSEG_MBYTES 0x50 + +#define SMRAMC 0x9d +#define G_SMRAME (1 << 3) +#define D_LCK (1 << 4) +#define D_CLS (1 << 5) +#define D_OPEN (1 << 6) +#define ESMRAMC 0x9e +#define T_EN (1 << 0) +#define TSEG_SZ_MASK (3 << 1) +#define H_SMRAME (1 << 7) + +void smm_region(uintptr_t *start, size_t *size) +{ + uint8_t esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + + switch ((esmramc & TSEG_SZ_MASK) >> 1) { + case 0: + *size = 1 * MiB; + break; + case 1: + *size = 2 * MiB; + break; + case 2: + *size = 8 * MiB; + break; + default: + *size = pci_read_config16(PCI_DEV(0, 0, 0), EXT_TSEG_MBYTES) * MiB; + } + + *start = qemu_get_memory_size() * KiB - *size; + printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %zu MiB\n", *start, *size / MiB); +}
Slava K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11: Hello,
This commit breaks FreeBSD support in qemu Q35. Very easy to reproduce; I'm using the freebsd13-bootonly ISO (12.x does not boot either, same issue) and get a panic immediately after bootloader prompt. Happens every time, with this commit and every one I tried after. Tried different SeaBIOS versions, including 1.16 latest. Works OK with commit prior to this one. This does not impact qemu i440fx.
The panic error is: `panic: running without device atpic requires a local APIC`
My defconfig:
``` CONFIG_USE_OPTION_TABLE=y CONFIG_CBFS_SIZE=0x0100000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="PlanetSlav" # CONFIG_POST_IO is not set # CONFIG_POST_DEVICE is not set CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y # CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="IntelVPS" # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_COREBOOT_ROMSIZE_KB_1024=y CONFIG_MAINBOARD_SERIAL_NUMBER="9671111" CONFIG_SEABIOS_MASTER=y ```
Also, I'm not sure if it's directly related to this, but a reddit user on /r/freebsd has also reported FreeBSD is not booting for him on T440p, also using SeaBIOS payload. Just throwing this out there in case a similar fix was commited to T440p board at some point? (I haven't looked for it specifically). Please let me know if you require any additional information for this or if I should submit a bug report somewhere.
Thank you
Attention is currently required from: Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
Hello, […]
Hi Slava,
can you tell us what ISO you used exactly and your QEMU command line, please. I just tried `FreeBSD-13.0-RELEASE-amd64-bootonly.iso` and it boots with the fol- lowing command line: $ qemu-system-x86_64 -M q35 -bios build/coreboot.rom -hda /tmp/FreeBSD-13.0-RELEASE-amd64-bootonly.iso
(the same didn't work for i386, but because SeaBIOS had trouble detecting the ISO?)
Attention is currently required from: Arthur Heymans. Slava K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48236 )
Change subject: mb/emulation/qemu-q35: Account for TSEG ......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
Hi Slava, […]
Hi Nico, thank you for looking into this.
I'm using the `FreeBSD-13.0-RELEASE-amd64-bootonly.iso` ISO
I'm using the following qemu command: $ qemu-system-x86_64 -bios coreboot.rom -serial stdio -M q35 -accel kvm -cpu host -m 1024 -curses -cdrom FreeBSD-13.0-RELEASE-amd64-bootonly.iso -drive file=testvm.img,media=disk,if=virtio -vnc :34001
QEMU version in case it's relevant: $ qemu-system-x86_64 --version QEMU emulator version 6.1.0 (qemu-6.1.0-10.fc35) Copyright (c) 2003-2021 Fabrice Bellard and the QEMU Project developers
I tried the qemu command you provided (I had to change hda to drive; it didn't let me boot raw iso with hda and also need the VNC switch to get a display) and it still fails.
Just to clarify, the error appears AFTER selecting the boot option in the FreeBSD bootloader. The loader loads fine, the error appears before getting to the actual installation prompt (blue TUI menu). Let me know if you require any additional information.
Thank you
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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build bot (Jenkins) (Code Review)
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Nico Huber (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)
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Slava K (Code Review)