Attention is currently required from: Michał Żygowski, Michał Kopeć, Paul Menzel, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59808 )
Change subject: northbridge/amd/pi/00730F01: enable PARALLEL_MP ......................................................................
Patch Set 5:
(1 comment)
File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/59808/comment/b3b23bc0_766e0306 PS4, Line 900: /* The flash is now no longer cacheable. Reset to WP for performance. */ : mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, : MTRR_TYPE_WRPROT);
Done
All BSP MTRRs are copied to the APs. Before loading the payload this MTRR is removed only the BSP which causes MTRR inconsistency because then the APs still have that WP MTRR set. APs don't need this, as all the code gets executed in dram anyway. post_mp_init might be an option but it boils down to the same as calling it after the mp init and it's consistent with other soc code.
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Arthur Heymans (Code Review)