[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event

[Jérémy Compostella (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Karthik Ramasubramanian, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik.

Jérémy Compostella has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86169?usp=email )

Change subject: soc/intel/common/block/cse: Add API to match current PM event
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Patch Set 2:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86169/comment/ee1980b0_d7efd8ce?usp... :
PS1, Line 9: Introduce an API to read the CSME host firmware status register for
nit: Introduce an API to read the CSME (Converged Security and Management Engine) host firmware status register to obtain the current Power Management event and compare it with a specified input event.

File src/soc/intel/common/block/cse/cse.c:

https://review.coreboot.org/c/coreboot/+/86169/comment/7a616d50_0dd6baff?usp... :
PS1, Line 302: #define ME_HFSTS2_CUR_PM_EVENT_MASK (0xF << ME_HFSTS2_CUR_PM_EVENT_SHIFT)
Usually coreboot uses lower case for hexadecimal constant values.

https://review.coreboot.org/c/coreboot/+/86169/comment/3736bf94_1a9eeb42?usp... :
PS1, Line 303: static uint8_t cse_get_hfs2_current_pm_event(void)
nit: An empty line would be nice.

File src/soc/intel/common/block/include/intelblocks/cse.h:

https://review.coreboot.org/c/coreboot/+/86169/comment/35416898_ace2048d?usp... :
PS1, Line 387: 	PWR_CYCLE_RESET_CMOFF = 0xB,
Usually coreboot uses lower case for hexadecimal constant values.