[M] Change in coreboot[master]: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Paul Menzel, Angel Pons, Jonathon Hall, Felix Held.

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74363 )

Change subject: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2
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Patch Set 6: Code-Review+1

(1 comment)

File src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c:

https://review.coreboot.org/c/coreboot/+/74363/comment/3d6d3543_d3cc3f4c 
PS5, Line 25: 	const pnp_devfn_t ec_rtct_dev = PNP_DEV(0x4E, IT8528E_RTCT);
> Thank you, good catch!  Checked this out, this base address is the default for the SuperIO, so the o […]

For Super-IOs many configuration bits are maintained over resets and even over the loss of V_stb rail (ACPI mechanical power-off G3?). Not sure about this ITE part.

I would not rely on the default being correct here and I don't remember how our bootblocks and vboot behave on CMOS errors. You might hit a reboot loop if you cannot access CMOS bank1 if the LDN in question is disabled or decodes a different base. And you may need a hard power toggle (like remove V_rtc lithium cell) to recover.