Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20472
Change subject: nb/intel/sandybridge/peg: Add PEG code ......................................................................
nb/intel/sandybridge/peg: Add PEG code
* Add ACPI code for PEG. * Add PCIe driver for PEG.
Change-Id: I80a106b1f969103206f24dc5c4b268503acfa81f Signed-off-by: Patrick Rudolph siro@das-labor.org --- M src/northbridge/intel/sandybridge/Makefile.inc A src/northbridge/intel/sandybridge/acpi/peg.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl A src/northbridge/intel/sandybridge/pcie.c 4 files changed, 137 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/20472/1
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 846d31b..a2ab06d 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -17,6 +17,7 @@
ramstage-y += ram_calc.c ramstage-y += northbridge.c +ramstage-y += pcie.c ramstage-y += gma.c ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl new file mode 100644 index 0000000..18e3ff2 --- /dev/null +++ b/src/northbridge/intel/sandybridge/acpi/peg.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph siro@das-labor.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PEGP) +{ + Name (_ADR, 0x00010000) + + // PCI Interrupt Routing. + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0 } + }) + } + } + + Device (DEV0) { + Name(_ADR, 0x00000000) + } +} diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 609106f..301ee8a 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -16,6 +16,7 @@
#include "../sandybridge.h" #include "hostbridge.asl" +#include "peg.asl"
/* PCI Device Resource Consumption */ Device (PDRC) diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c new file mode 100644 index 0000000..ba8da43 --- /dev/null +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph siro@das-labor.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> +#include <southbridge/intel/common/pciehp.h> +#include "sandybridge.h" + +static void pcie_disable(device_t dev) +{ + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + + dev->enabled = 0; +} + +static const char *pcie_acpi_name(device_t dev) +{ + ASSERT(dev); + ASSERT(dev->bus); + + if (dev->bus->secondary == 0 && + PCI_SLOT(dev->path.pci.devfn) == 0x01 && + PCI_FUNC(dev->path.pci.devfn) == 0x00) + return "PEGP"; + + ASSERT(dev->bus->dev); + ASSERT(dev->bus->dev->bus); + + if (dev->bus->dev->bus->secondary == 0 && + PCI_SLOT(dev->bus->dev->path.pci.devfn) == 0x01 && + PCI_FUNC(dev->bus->dev->path.pci.devfn) == 0x00 && + PCI_SLOT(dev->path.pci.devfn) == 0x00 && + PCI_FUNC(dev->path.pci.devfn) == 0x00) + return "DEV0"; + + return NULL; +} + + +static void +pcie_set_subsystem(device_t dev, unsigned int vendor, unsigned int device) +{ + /* NOTE: This is not the default position! */ + if (!vendor || !device) + pci_write_config32(dev, 0x94, + pci_read_config32(dev, 0)); + else + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations pci_ops = { + .set_subsystem = pcie_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .disable = pcie_disable, + .ops_pci = &pci_ops, + .acpi_name = pcie_acpi_name, +}; + +static const unsigned short pci_device_ids[] = { 0x0101, 0x0105, 0x0109, 0x010d, + 0x0151, 0x0155, 0x0159, 0x015d, + 0 }; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};
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Patrick Rudolph (Code Review)