Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17854
-gerrit
commit 5532c6704cf565867b96c7c5c374a48368f02dff Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Tue Dec 13 17:37:17 2016 +0200
[NOTFORMERGE] asus/p5kpl-vm NetBurst test
also needs https://review.coreboot.org/#/c/17832/
Change-Id: If3e1df39e8afddc4bbafe0c26e6b5a3f4a0230d3 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/asus/p5gc-mx/romstage.c | 77 +++++++++++++++++++-------------- src/northbridge/intel/i945/bootblock.c | 3 +- src/northbridge/intel/i945/early_init.c | 2 +- src/northbridge/intel/i945/i945.h | 8 ++-- 4 files changed, 51 insertions(+), 39 deletions(-)
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index b495ebf..44ef5d2 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -47,52 +47,60 @@ void setup_ich7_gpios(void) /* TODO: This is highly board specific and should be moved */ printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ - outl(0x1f3dffc1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xe0e8f7c2, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xe2febb7e, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0xdf3df7c3, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0x20e8fac3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xe2eefa7f, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ /* Output Control Registers */ outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ /* Input Control Registers */ - outl(0x00006000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x00030033, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ + outl(0x000300f3, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ }
-static void setup_sio_gpio(u32 fsb) +static void setup_sio_gpio(u8 bsel) { - printk(BIOS_DEBUG, "Setting up Superio GPIOs\n"); + int need_reset = 0; + u8 reg, old_reg;
pnp_enter_ext_func_mode(GPIO_DEV); pnp_set_logical_device(GPIO_DEV);
+ reg = 0x9a; + old_reg = pnp_read_config(GPIO_DEV, 0x2c); + pnp_write_config(GPIO_DEV, 0x2c, reg); + need_reset = (reg != old_reg); + pnp_write_config(GPIO_DEV, 0x2c, 0x9a); - pnp_write_config(GPIO_DEV, 0x30, 0x0e); - pnp_write_config(GPIO_DEV, 0xe0, 0xde); + pnp_write_config(GPIO_DEV, 0x30, 0x07); + pnp_write_config(GPIO_DEV, 0xe3, 0xfb); pnp_write_config(GPIO_DEV, 0xf0, 0xf3); + pnp_write_config(GPIO_DEV, 0xf3, 0x09); + pnp_write_config(GPIO_DEV, 0xf4, 0x9e);
- switch (fsb) { - case 5: /* 400MHz */ - case 1: /* 553MHz */ - pnp_write_config(GPIO_DEV, 0xf1, 0x08); - break; - case 2: /* 800MHz */ - pnp_write_config(GPIO_DEV, 0xf1, 0x0c); - break; - case 0: /* 1067MHz */ - case 4: /* 1333MHz */ - case 6: /* 1600MHz */ - pnp_write_config(GPIO_DEV, 0xf1, 0x00); - break; - } + reg = (bsel & 3) << 2; + old_reg = pnp_read_config(GPIO_DEV, 0xf1); + pnp_write_config(GPIO_DEV, 0xf1, reg); + need_reset += ((reg & 0xc) != (old_reg & 0xc));
- pnp_write_config(GPIO_DEV, 0xf4, 0x80); - pnp_write_config(GPIO_DEV, 0xf5, 0x80); + reg = 0x60 | ((bsel >> 2) & 1); + old_reg = pnp_read_config(GPIO_DEV, 0xf5); + pnp_write_config(GPIO_DEV, 0xf5, reg); + need_reset += ((reg & 0x1) != (old_reg & 0x1));
pnp_exit_ext_func_mode(GPIO_DEV); + + if (need_reset) { + int i=1000; + while (i--) outb(i & 0xff, 0x80); + outb(0x2, 0xcf9); + outb(0xe, 0xcf9); + halt(); + } }
-static u32 msr_get_fsb(void) +static u8 msr_get_bsel(void) { u8 fsbcfg; msr_t msr; @@ -123,8 +131,6 @@ static void ich7_enable_lpc(void)
/* range 0x15e0 - 0x10ef */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x40291); - - }
static void rcba_config(void) @@ -197,18 +203,22 @@ void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0, boot_mode = 0; /* FIXME this only works for core 2 CPUs */ + u8 c_bsel, m_bsel;
if (bist == 0) enable_lapic();
ich7_enable_lpc();
+ c_bsel = msr_get_bsel(); + setup_sio_gpio(c_bsel); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
/* Set up the console */ console_init();
- setup_sio_gpio(msr_get_fsb()); + printk(BIOS_DEBUG, "CPU BSEL straps = %x\n", c_bsel);
/* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -223,10 +233,11 @@ void mainboard_romstage_entry(unsigned long bist) */ i945_early_initialization();
- if ((MCHBAR32(CLKCFG) & 7) != msr_get_fsb()) { - printk(BIOS_DEBUG, "Setting BSEL straps, resetting...\n"); - outb(0x2, 0xcf9); - outb(0xe, 0xcf9); + m_bsel = MCHBAR32(CLKCFG) & 7; + printk(BIOS_DEBUG, "MCH BSEL straps = %x\n", m_bsel); + + if (m_bsel != c_bsel) { + printk(BIOS_DEBUG, "Failed BSEL configuration\n"); halt(); }
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 4571446..6c75c13 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -1,7 +1,7 @@ #include <arch/io.h>
/* Just re-define this instead of including i945.h. It blows up romcc. */ -#define PCIEXBAR 0x48 +#define PCIEXBAR 0x60
static void bootblock_northbridge_init(void) { @@ -21,4 +21,5 @@ static void bootblock_northbridge_init(void) */ reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, 0x0); } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 16ae55f..bdbda99 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -178,7 +178,7 @@ static void i945_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); +// pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
/* vram size from cmos option */ if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 1686acc..918c8d3 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -47,10 +47,10 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */
#define EPBAR 0x40 -#define MCHBAR 0x44 -#define PCIEXBAR 0x48 -#define DMIBAR 0x4c -#define X60BAR 0x60 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +//#define X60BAR 0x60
#define GGC 0x52 /* GMCH Graphics Control */
-
Kyösti Mälkki