[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Keith Hui (Code Review)]

Attention is currently required from: Bill XIE.

Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
......................................................................

Patch Set 3:

(1 comment)

File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:

https://review.coreboot.org/c/coreboot/+/85413/comment/de6780b5_cc6d222a?usp... :
PS2, Line 77: {7, 34, 20, -1}
> Thanks Bill. Got it. Will take a look.

I saw your dumps and honestly I can't see I missed anything. My card detect logic at PCIEX1_2 appears to be correct. Let's go back to coreboot with this patch. We need to see what differs between vendor dump and coreboot dump, all with your Marvell SATA card in PCIEX1_2. I'd also like to get your console log to see what ramstage is seeing when scanning the PCIe bus.

Failing these, we'll need to bring in more eyes.