Change in coreboot[master]: soc/amd/cezanne: Add SPI registers - coreboot-gerrit

9 Feb 2021


      Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held.
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50445 )
Change subject: soc/amd/cezanne: Add SPI registers
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Patch Set 2: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3ef4c51ef6d656b3b035d97a56b1875b40e89210
Gerrit-Change-Number: 50445
Gerrit-PatchSet: 2
Gerrit-Owner: Raul Rangel rrangel@chromium.org
Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de
Gerrit-Reviewer: Jason Glenesk jason.glenesk@gmail.com
Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com
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Gerrit-Comment-Date: Tue, 09 Feb 2021 21:10:17 +0000
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