Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45356 )
Change subject: nb/intel/sandybridge: Introduce memmap.h ......................................................................
nb/intel/sandybridge: Introduce memmap.h
Move all memory map definitions into a separate header.
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.
Change-Id: I7f2ff2a5cee8bf12e5dca74ff9f0b1a44e26cded Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/northbridge/intel/sandybridge/memmap.h M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 15 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45356/1
diff --git a/src/northbridge/intel/sandybridge/memmap.h b/src/northbridge/intel/sandybridge/memmap.h new file mode 100644 index 0000000..9825125 --- /dev/null +++ b/src/northbridge/intel/sandybridge/memmap.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__ +#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__ + +/* Northbridge BARs */ +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#define GFXVT_BASE 0xfed90000ULL +#define VTVC0_BASE 0xfed91000ULL + +#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 7b008e8..9db5ae3 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -20,13 +20,7 @@ #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6)
-/* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ - -#define GFXVT_BASE 0xfed90000ULL -#define VTVC0_BASE 0xfed91000ULL +#include "memmap.h"
/* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45356 )
Change subject: nb/intel/sandybridge: Introduce memmap.h ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45356 )
Change subject: nb/intel/sandybridge: Introduce memmap.h ......................................................................
nb/intel/sandybridge: Introduce memmap.h
Move all memory map definitions into a separate header.
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.
Change-Id: I7f2ff2a5cee8bf12e5dca74ff9f0b1a44e26cded Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45356 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/northbridge/intel/sandybridge/memmap.h M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 15 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/memmap.h b/src/northbridge/intel/sandybridge/memmap.h new file mode 100644 index 0000000..9825125 --- /dev/null +++ b/src/northbridge/intel/sandybridge/memmap.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__ +#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__ + +/* Northbridge BARs */ +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#define GFXVT_BASE 0xfed90000ULL +#define VTVC0_BASE 0xfed91000ULL + +#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 7b008e8..9db5ae3 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -20,13 +20,7 @@ #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6)
-/* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ - -#define GFXVT_BASE 0xfed90000ULL -#define VTVC0_BASE 0xfed91000ULL +#include "memmap.h"
/* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45356 )
Change subject: nb/intel/sandybridge: Introduce memmap.h ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/20175 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20174 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/20173 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20172 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/20171 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/20179 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/20178 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/20177 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20176
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
-
Patrick Georgi (Code Review)
-
Tim Wawrzynczak (Code Review)