Change in coreboot[master]: northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in ho...
Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41977 )
Change subject: northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl ......................................................................
northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly.
Change-Id: I1fb52a42e84130d973e0970024e263f443aa0b89 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 6 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/41977/1
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 8fbfabf..dd4b79a 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -425,13 +425,17 @@
// Fix up PCI memory region // Start with Top of Lower Usable DRAM - Local0 = ^MCHC.TLUD + // Lower 20 bits of TOLUD register need to be masked since they contain lock and + // reserved bits. + Local0 = ^MCHC.TLUD & (0xfff << 20) Local1 = ^MCHC.MEBA
// Check if ME base is equal If (Local0 == Local1) { // Use Top Of Memory instead - Local0 = ^MCHC.TOM + // Lower 20 bits of TOM register need to be masked since they contain lock and + // reserved bits. + Local0 = ^MCHC.TOM & (0x7ffff << 20) }
PMIN = Local0
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41977 )
Change subject: northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41977 )
Change subject: northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl ......................................................................
northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly.
Change-Id: I1fb52a42e84130d973e0970024e263f443aa0b89 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41977 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 6 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 8fbfabf..dd4b79a 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -425,13 +425,17 @@
// Fix up PCI memory region // Start with Top of Lower Usable DRAM - Local0 = ^MCHC.TLUD + // Lower 20 bits of TOLUD register need to be masked since they contain lock and + // reserved bits. + Local0 = ^MCHC.TLUD & (0xfff << 20) Local1 = ^MCHC.MEBA
// Check if ME base is equal If (Local0 == Local1) { // Use Top Of Memory instead - Local0 = ^MCHC.TOM + // Lower 20 bits of TOM register need to be masked since they contain lock and + // reserved bits. + Local0 = ^MCHC.TOM & (0x7ffff << 20) }
PMIN = Local0
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41977 )
Change subject: northbridge/intel/haswell: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4807 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4806 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4805 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4804
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Furquan Shaikh (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)