Change in coreboot[master]: mb/intel/adlrvp: Configure EC in RW GPIO

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58099 )

Change subject: mb/intel/adlrvp: Configure EC in RW GPIO
......................................................................

mb/intel/adlrvp: Configure EC in RW GPIO

EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO
can be used to check EC status
trusted (LOW: in RO) or untrusted (HIGH: in RW).

Branch=none
Bug=none
Test=Issue manual recovery and confirm DUT is entering recovery mode on
ADL-M RVP.

Signed-off-by: Anil Kumar 
Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58099
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/adlrvp/early_gpio.c
M src/mainboard/intel/adlrvp/early_gpio_m.c
M src/mainboard/intel/adlrvp/gpio.c
M src/mainboard/intel/adlrvp/include/baseboard/gpio.h
5 files changed, 13 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c
index d963c73..244b942 100644
--- a/src/mainboard/intel/adlrvp/chromeos.c
+++ b/src/mainboard/intel/adlrvp/chromeos.c
@@ -12,9 +12,12 @@
    	{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
    	{-1, ACTIVE_HIGH, 0, "power"},
    	{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
-		{-1, ACTIVE_HIGH, 0, "EC in RW"},
+		{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
    };
-	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+	if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC))
+		lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+	else
+		lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios) - 1);
 }

#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES)
diff --git a/src/mainboard/intel/adlrvp/early_gpio.c b/src/mainboard/intel/adlrvp/early_gpio.c
index 7576ff1..68d69af 100644
--- a/src/mainboard/intel/adlrvp/early_gpio.c
+++ b/src/mainboard/intel/adlrvp/early_gpio.c
@@ -16,6 +16,9 @@
    /* SMB_DATA */
    PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),

+	/* EC_IN_RW */
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+
    /* CPU PCIe VGPIO for RP0 */
    PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1),
    PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1),
diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c
index 915240c..3798593 100644
--- a/src/mainboard/intel/adlrvp/early_gpio_m.c
+++ b/src/mainboard/intel/adlrvp/early_gpio_m.c
@@ -17,6 +17,9 @@
    /* H13 : CPU_SSD_RST# */
    PAD_CFG_GPO(GPP_H13, 0, PLTRST),

+	/* EC_IN_RW */
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+
    /* CPU PCIe VGPIO for RP0 */
    PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1),
    PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1),
diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c
index 1996683..c4d946b 100644
--- a/src/mainboard/intel/adlrvp/gpio.c
+++ b/src/mainboard/intel/adlrvp/gpio.c
@@ -38,8 +38,6 @@
    PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
    /* THC1_SPI2_INTB */
    PAD_CFG_GPI(GPP_E17, NONE, PLTRST),
-	/* EC_SMI_N */
-	PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, NONE),
    /* EC_SLP_S0_CS_N */
    PAD_CFG_GPO(GPP_F9, 1, PLTRST),
    /* WIFI RF KILL */
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h
index de0adf6..9a1c585 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h
@@ -12,4 +12,6 @@
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
 #define GPE_EC_WAKE	GPE0_LAN_WAK

+#define GPIO_EC_IN_RW	GPP_E7
+
 #endif /* __BASEBOARD_GPIO_H__ */