[XS] Change in coreboot[main]: soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD

[Subrata Banik (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Pranava Y N, Subrata Banik.

Hello Intel coreboot Reviewers, Kapil Porwal, Pranava Y N, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/87266?usp=email

to look at the new patch set (#2).

Change subject: soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD
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soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD

This commit introduces a conditional bypass for ME state setting,
potentially reducing CBFS traversal time when searching for the
`option/me_state` file.

TEST=Able to build and boot google/fatcat.

Change-Id: I43f5daab450989307d9b3529949e9f03cba4404d
Signed-off-by: Subrata Banik 
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/87266/2