Rocky Phagura has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41680 )
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
soc/intel/xeon_sp: Early programming of ACPI bar
ACPI bar was not programmed previously for which is needed to enable SMI's and to check SMI status registers.
TEST=build for Tiogapass and checked ACPI base, able to enable SMIs and check status registers
Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379 Signed-off-by: Rocky Phagura rphagura@fb.com --- M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/bootblock.c A src/soc/intel/xeon_sp/include/soc/bootblock.h A src/soc/intel/xeon_sp/include/soc/pch.h M src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/pch.c 6 files changed, 123 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/41680/1
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 7950b81..9589e5a 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -5,7 +5,7 @@ subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx
-bootblock-y += bootblock.c spi.c lpc.c gpio.c +bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 7f14be6..72d9742 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -9,6 +9,7 @@ #include <cpu/x86/mtrr.h> #include <intelblocks/lpc_lib.h> #include <soc/pci_devs.h> +#include <soc/bootblock.h>
const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -53,4 +54,5 @@ { if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); + bootblock_pch_init(); } diff --git a/src/soc/intel/xeon_sp/include/soc/bootblock.h b/src/soc/intel/xeon_sp/include/soc/bootblock.h new file mode 100644 index 0000000..4b1bae8 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/bootblock.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _SOC_SKYLAKE_BOOTBLOCK_H_ +#define _SOC_SKYLAKE_BOOTBLOCK_H_ + +#include <intelblocks/systemagent.h> + +/* Bootblock pre console init programming */ +void bootblock_cpu_init(void); +void bootblock_pch_early_init(void); + +/* Bootblock post console init programming */ +void i2c_early_init(void); +void bootblock_pch_init(void); +void pch_early_iorange_init(void); +void report_platform_info(void); +void report_memory_config(void); + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/pch.h b/src/soc/intel/xeon_sp/include/soc/pch.h new file mode 100644 index 0000000..72150f8 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pch.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef _SOC_PCH_H_ +#define _SOC_PCH_H_ + +#include <device/device.h> + +#if ENV_RAMSTAGE +void pch_disable_devfn(struct device *dev); +#endif + +#endif /* _SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index 74343f8..d3bad1b 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -3,18 +3,28 @@ #ifndef _SOC_PMC_H_ #define _SOC_PMC_H_
-/* PCI Configuration Space (D31:F2): PMC */ -#define PMC_ACPI_CNT 0x44 + /* PCI Configuration Space (D31:F2): PMC */ +#define ABASE 0x40 +#define ACTL 0x44 +#define PMC_ACPI_CNT 0x44 +#define PWRM_EN (1 << 8) +#define ACPI_EN (1 << 7) +#define SCI_IRQ_SEL (7 << 0) +#define SCI_IRQ_ADJUST 0
-#define SCI_IRQ_SEL (7 << 0) -#define SCIS_IRQ9 0 -#define SCIS_IRQ10 1 -#define SCIS_IRQ11 2 -#define SCIS_IRQ20 4 -#define SCIS_IRQ21 5 -#define SCIS_IRQ22 6 -#define SCIS_IRQ23 7 +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define PWRMBASE 0x48 +#define GEN_PMCON_A 0xa0 +#define SMI_LOCK (1 << 4) +#define GEN_PMCON_B 0xa4 +#define SLP_STR_POL_LOCK (1 << 18) +#define ACPI_BASE_LOCK (1 << 17)
-#define SCI_IRQ_ADJUST 0
#endif diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c new file mode 100644 index 0000000..d6c1c4b --- /dev/null +++ b/src/soc/intel/xeon_sp/pch.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/pci_ops.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <intelblocks/cse.h> +#include <intelblocks/fast_spi.h> +#include <intelblocks/itss.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/p2sb.h> +#include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> +#include <intelblocks/rtc.h> +#include <soc/bootblock.h> +#include <soc/iomap.h> +#include <soc/p2sb.h> +#include <soc/pch.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/pm.h> +#include <soc/pmc.h> +#include "../chip.h" +#include <console/console.h> + +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 + +static void soc_config_acpibase(void) +{ + uint32_t reg32; + + /* Disable ABASE in PMC Device first before changing Base Address */ + reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); + + /* Program ACPI Base */ + pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); + + /* Enable ACPI in PMC */ + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); + + uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE); + printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data); + /* + * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] + * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] + */ + reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); + pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); + pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); +} + +void bootblock_pch_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT + */ + soc_config_acpibase(); + + enable_rtc_upper_bank(); +}
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41680 )
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
Patch Set 1:
(3 comments)
Please include only what you use
https://review.coreboot.org/c/coreboot/+/41680/1/src/soc/intel/xeon_sp/inclu... File src/soc/intel/xeon_sp/include/soc/bootblock.h:
https://review.coreboot.org/c/coreboot/+/41680/1/src/soc/intel/xeon_sp/inclu... PS1, Line 2: /* This file is part of the coreboot project. */ please remove
https://review.coreboot.org/c/coreboot/+/41680/1/src/soc/intel/xeon_sp/pch.c File src/soc/intel/xeon_sp/pch.c:
https://review.coreboot.org/c/coreboot/+/41680/1/src/soc/intel/xeon_sp/pch.c... PS1, Line 2: * This file is part of the coreboot project. */ Please remove
https://review.coreboot.org/c/coreboot/+/41680/1/src/soc/intel/xeon_sp/pch.c... PS1, Line 4: #include <device/pci_ops.h> : #include <device/device.h> : #include <device/pci_def.h> : #include <intelblocks/cse.h> : #include <intelblocks/fast_spi.h> : #include <intelblocks/itss.h> : #include <intelblocks/lpc_lib.h> : #include <intelblocks/p2sb.h> : #include <intelblocks/pcr.h> : #include <intelblocks/pmclib.h> : #include <intelblocks/rtc.h> : #include <soc/bootblock.h> : #include <soc/iomap.h> : #include <soc/p2sb.h> : #include <soc/pch.h> : #include <soc/pci_devs.h> : #include <soc/pcr_ids.h> : #include <soc/pm.h> : #include <soc/pmc.h> : #include "../chip.h" : #include <console/console.h> are you using all of them ?
Please clean-up.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41680 )
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
Patch Set 1:
(3 comments)
Please mention, if you copied this from some other device.
https://review.coreboot.org/c/coreboot/+/41680/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41680/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/xeon_sp: Early programming of ACPI bar Please make that a statement by adding a verb (in imperative mood). Maybe:
soc/intel/xeon_sp: Program ACPI bar early
See `git log --oneline` for more examples.
https://review.coreboot.org/c/coreboot/+/41680/1//COMMIT_MSG@12 PS1, Line 12: checked check
https://review.coreboot.org/c/coreboot/+/41680/1//COMMIT_MSG@13 PS1, Line 13: status registers Any changes in the log messages?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Jonathan Zhang, David Hendricks, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41680
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
soc/intel/xeon_sp: Early programming of ACPI bar
ACPI bar was not programmed previously for which is needed to enable SMI's and to check SMI status registers. Code is referenced from Skylake.
TEST=build for Tiogapass and checked ACPI base, able to enable SMIs and check status registers
Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379 Signed-off-by: Rocky Phagura rphagura@fb.com --- M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/bootblock.c A src/soc/intel/xeon_sp/include/soc/bootblock.h A src/soc/intel/xeon_sp/include/soc/pch.h M src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/pch.c 6 files changed, 107 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/41680/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Jonathan Zhang, David Hendricks, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41680
to look at the new patch set (#3).
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
soc/intel/xeon_sp: Early programming of ACPI bar
ACPI bar was not programmed previously for which is needed to enable SMI's and to check SMI status registers. Code is referenced from Skylake.
TEST=build for Tiogapass and check ACPI base. Log message will now show pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing to io port 0x500.
Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379 Signed-off-by: Rocky Phagura rphagura@fb.com --- M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/bootblock.c A src/soc/intel/xeon_sp/include/soc/bootblock.h A src/soc/intel/xeon_sp/include/soc/pch.h M src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/pch.c 6 files changed, 107 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/41680/3
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41680 )
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41680/1/src/soc/intel/xeon_sp/inclu... File src/soc/intel/xeon_sp/include/soc/bootblock.h:
https://review.coreboot.org/c/coreboot/+/41680/1/src/soc/intel/xeon_sp/inclu... PS1, Line 2: /* This file is part of the coreboot project. */
please remove
Done
https://review.coreboot.org/c/coreboot/+/41680/1/src/soc/intel/xeon_sp/pch.c File src/soc/intel/xeon_sp/pch.c:
https://review.coreboot.org/c/coreboot/+/41680/1/src/soc/intel/xeon_sp/pch.c... PS1, Line 2: * This file is part of the coreboot project. */
Please remove
Done
https://review.coreboot.org/c/coreboot/+/41680/1/src/soc/intel/xeon_sp/pch.c... PS1, Line 4: #include <device/pci_ops.h> : #include <device/device.h> : #include <device/pci_def.h> : #include <intelblocks/cse.h> : #include <intelblocks/fast_spi.h> : #include <intelblocks/itss.h> : #include <intelblocks/lpc_lib.h> : #include <intelblocks/p2sb.h> : #include <intelblocks/pcr.h> : #include <intelblocks/pmclib.h> : #include <intelblocks/rtc.h> : #include <soc/bootblock.h> : #include <soc/iomap.h> : #include <soc/p2sb.h> : #include <soc/pch.h> : #include <soc/pci_devs.h> : #include <soc/pcr_ids.h> : #include <soc/pm.h> : #include <soc/pmc.h> : #include "../chip.h" : #include <console/console.h>
are you using all of them ? […]
Done
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41680 )
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/inclu... File src/soc/intel/xeon_sp/include/soc/bootblock.h:
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/inclu... PS3, Line 3: _SOC_SKYLAKE_BOOTBLOCK_H_ not nice _SOC_SKYLAKE_BOOTBLOCK_H_ already exists in src/soc/intel/skylake/include/soc/bootblock.h may be _XEON_SP_BOOTBLOCK_H_?
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/inclu... PS3, Line 8: /* Bootblock pre console init programming */ : void bootblock_cpu_init(void); : void bootblock_pch_early_init(void); : : /* Bootblock post console init programming */ : void i2c_early_init(void); In this patch, only the bootblock_pch_init function is added, others aren't needed.
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/inclu... PS3, Line 15: void pch_early_iorange_init(void); : void report_platform_info(void); : void report_memory_config(void); Do we really need these function now?
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/pch.c File src/soc/intel/xeon_sp/pch.c:
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/pch.c... PS3, Line 51: enable_rtc_upper_bank(); I think it would be better to do this in a separate patch.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41680 )
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
Patch Set 3: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/pch.c File src/soc/intel/xeon_sp/pch.c:
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/pch.c... PS3, Line 39: ) unnecessary parentheses
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/pch.c... PS3, Line 39: 0x3f #define PCR_DMI_ACPIBA_ADDR72MASK 0x3f
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41680 )
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41680/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41680/3//COMMIT_MSG@10 PS3, Line 10: Skylake Let's clarify here:
"The architecture of the Lewisburg PCH is very similar to the Sunrise Point. Therefore, we can use the code from soc/intel/skylake."
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maxim Polyakov, Jonathan Zhang, David Hendricks, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41680
to look at the new patch set (#4).
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
soc/intel/xeon_sp: Early programming of ACPI bar
ACPI bar was not programmed previously for which is needed to enable SMI's and to check SMI status registers. The architecture of Lewisburg PCH is very similar to SunrisePoint PCH thus we can use code from soc/intel/skylake.
TEST=build for Tiogapass and check ACPI base. Log message will now show pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing to io port 0x500.
Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379 Signed-off-by: Rocky Phagura rphagura@fb.com --- M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/bootblock.c A src/soc/intel/xeon_sp/include/soc/bootblock.h A src/soc/intel/xeon_sp/include/soc/pch.h M src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/pch.c 6 files changed, 97 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/41680/4
Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41680 )
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
Patch Set 4:
(6 comments)
https://review.coreboot.org/c/coreboot/+/41680/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41680/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/xeon_sp: Early programming of ACPI bar
Please make that a statement by adding a verb (in imperative mood). Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/41680/1//COMMIT_MSG@12 PS1, Line 12: checked
check
Done
https://review.coreboot.org/c/coreboot/+/41680/1//COMMIT_MSG@13 PS1, Line 13: status registers
Any changes in the log messages?
Done...added more information for log.
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/inclu... File src/soc/intel/xeon_sp/include/soc/bootblock.h:
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/inclu... PS3, Line 3: _SOC_SKYLAKE_BOOTBLOCK_H_
not nice […]
Ack
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/inclu... PS3, Line 8: /* Bootblock pre console init programming */ : void bootblock_cpu_init(void); : void bootblock_pch_early_init(void); : : /* Bootblock post console init programming */ : void i2c_early_init(void);
In this patch, only the bootblock_pch_init function is added, others aren't needed.
Ack
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/inclu... PS3, Line 15: void pch_early_iorange_init(void); : void report_platform_info(void); : void report_memory_config(void);
Do we really need these function now?
Ack
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41680 )
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
Patch Set 4: Code-Review+2
(3 comments)
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/pch.c File src/soc/intel/xeon_sp/pch.c:
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/pch.c... PS3, Line 39: 0x3f
#define PCR_DMI_ACPIBA_ADDR72MASK 0x3f
I meant that you use PCR_DMI_ACPIBA_ADDR72MASK (as define) instead of this magic 0x3f value. But this is just a recommendation.
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/pch.c... PS3, Line 39: )
unnecessary parentheses
Done
https://review.coreboot.org/c/coreboot/+/41680/3/src/soc/intel/xeon_sp/pch.c... PS3, Line 51: enable_rtc_upper_bank();
I think it would be better to do this in a separate patch.
Ack
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41680 )
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41680/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41680/3//COMMIT_MSG@10 PS3, Line 10: Skylake
Let's clarify here: […]
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41680 )
Change subject: soc/intel/xeon_sp: Early programming of ACPI bar ......................................................................
soc/intel/xeon_sp: Early programming of ACPI bar
ACPI bar was not programmed previously for which is needed to enable SMI's and to check SMI status registers. The architecture of Lewisburg PCH is very similar to SunrisePoint PCH thus we can use code from soc/intel/skylake.
TEST=build for Tiogapass and check ACPI base. Log message will now show pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing to io port 0x500.
Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379 Signed-off-by: Rocky Phagura rphagura@fb.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41680 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/bootblock.c A src/soc/intel/xeon_sp/include/soc/bootblock.h A src/soc/intel/xeon_sp/include/soc/pch.h M src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/pch.c 6 files changed, 97 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 7950b81..9589e5a 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -5,7 +5,7 @@ subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx
-bootblock-y += bootblock.c spi.c lpc.c gpio.c +bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 7f14be6..72d9742 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -9,6 +9,7 @@ #include <cpu/x86/mtrr.h> #include <intelblocks/lpc_lib.h> #include <soc/pci_devs.h> +#include <soc/bootblock.h>
const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -53,4 +54,5 @@ { if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); + bootblock_pch_init(); } diff --git a/src/soc/intel/xeon_sp/include/soc/bootblock.h b/src/soc/intel/xeon_sp/include/soc/bootblock.h new file mode 100644 index 0000000..6be4370 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/bootblock.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_XEON_SP_BOOTBLOCK_H_ +#define _SOC_XEON_SP_BOOTBLOCK_H_ + +#include "iomap.h" + +/* Bootblock post console init programming */ +void bootblock_pch_init(void); + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/pch.h b/src/soc/intel/xeon_sp/include/soc/pch.h new file mode 100644 index 0000000..84d5e48 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pch.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PCH_H_ +#define _SOC_PCH_H_ + +#include <device/device.h> + +#if ENV_RAMSTAGE +void pch_disable_devfn(struct device *dev); +#endif + +#endif /* _SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index 74343f8..d3bad1b 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -3,18 +3,28 @@ #ifndef _SOC_PMC_H_ #define _SOC_PMC_H_
-/* PCI Configuration Space (D31:F2): PMC */ -#define PMC_ACPI_CNT 0x44 + /* PCI Configuration Space (D31:F2): PMC */ +#define ABASE 0x40 +#define ACTL 0x44 +#define PMC_ACPI_CNT 0x44 +#define PWRM_EN (1 << 8) +#define ACPI_EN (1 << 7) +#define SCI_IRQ_SEL (7 << 0) +#define SCI_IRQ_ADJUST 0
-#define SCI_IRQ_SEL (7 << 0) -#define SCIS_IRQ9 0 -#define SCIS_IRQ10 1 -#define SCIS_IRQ11 2 -#define SCIS_IRQ20 4 -#define SCIS_IRQ21 5 -#define SCIS_IRQ22 6 -#define SCIS_IRQ23 7 +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define PWRMBASE 0x48 +#define GEN_PMCON_A 0xa0 +#define SMI_LOCK (1 << 4) +#define GEN_PMCON_B 0xa4 +#define SLP_STR_POL_LOCK (1 << 18) +#define ACPI_BASE_LOCK (1 << 17)
-#define SCI_IRQ_ADJUST 0
#endif diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c new file mode 100644 index 0000000..5427952 --- /dev/null +++ b/src/soc/intel/xeon_sp/pch.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <intelblocks/pcr.h> +#include <intelblocks/rtc.h> +#include <soc/bootblock.h> +#include <soc/pmc.h> +#include <console/console.h> + +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 + +static void soc_config_acpibase(void) +{ + uint32_t reg32; + + /* Disable ABASE in PMC Device first before changing Base Address */ + reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); + + /* Program ACPI Base */ + pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); + + /* Enable ACPI in PMC */ + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); + + uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE); + printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data); + /* + * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] + * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] + */ + reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1; + pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); + pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); +} + +void bootblock_pch_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT + */ + soc_config_acpibase(); +}
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HAOUAS Elyes (Code Review) -
Maxim Polyakov (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Rocky Phagura (Code Review)