Attention is currently required from: Shreesh Chhabbi, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Sukumar Ghorai, Raj Astekar, Patrick Rudolph.
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 )
Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
......................................................................
Patch Set 39:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49766/comment/dd8fa149_764e7a48
PS38, Line 21: Deepest state expected on tigerlake up3 based
: platforms is S0i3.1.
This is not correct. It is S0i3. […]
Ok correcting it.
https://review.coreboot.org/c/coreboot/+/49766/comment/5a0205d2_2f9bc325
PS38, Line 26: S0i3.1
Volteer can reach S0i3.1 only because it uses CNVi.
Got it. Thanks Furquan.
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Gerrit-Project: coreboot
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