HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41670 )
Change subject: src: Remove unused 'include <bootmode.h>' ......................................................................
src: Remove unused 'include <bootmode.h>'
Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/ec/google/chromeec/ec.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/skylake/chip.c 7 files changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/41670/1
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index b964581..6465960 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -3,7 +3,6 @@ #include <stdint.h> #include <string.h> #include <assert.h> -#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index a2b26ae..72c284f 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -2,7 +2,6 @@
#include <console/console.h> #include <commonlib/region.h> -#include <bootmode.h> #include <cf9_reset.h> #include <string.h> #include <arch/cpu.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 43858f5..1ec54b3 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -2,7 +2,6 @@
#include <console/console.h> #include <console/usb.h> -#include <bootmode.h> #include <cf9_reset.h> #include <string.h> #include <device/device.h> diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 1077824..3545d55 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -4,7 +4,6 @@ * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */
-#include <bootmode.h> #include <console/console.h> #include <device/device.h> #include <soc/addressmap.h> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2abeb3a..09537a1 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -4,7 +4,6 @@ #include <device/pci_ops.h> #include <arch/symbols.h> #include <assert.h> -#include <bootmode.h> #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 54d6134..3b7aa40 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -2,7 +2,6 @@
#include <stdint.h> #include <arch/romstage.h> -#include <bootmode.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index b14bb72..a1ef06e 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <fsp/api.h>
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41670 )
Change subject: src: Remove unused 'include <bootmode.h>' ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41670 )
Change subject: src: Remove unused 'include <bootmode.h>' ......................................................................
src: Remove unused 'include <bootmode.h>'
Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/41670 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/ec/google/chromeec/ec.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/skylake/chip.c 7 files changed, 0 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 034e931..233f61b 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -3,7 +3,6 @@ #include <stdint.h> #include <string.h> #include <assert.h> -#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index a2b26ae..72c284f 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -2,7 +2,6 @@
#include <console/console.h> #include <commonlib/region.h> -#include <bootmode.h> #include <cf9_reset.h> #include <string.h> #include <arch/cpu.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 43858f5..1ec54b3 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -2,7 +2,6 @@
#include <console/console.h> #include <console/usb.h> -#include <bootmode.h> #include <cf9_reset.h> #include <string.h> #include <device/device.h> diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 1077824..3545d55 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -4,7 +4,6 @@ * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */
-#include <bootmode.h> #include <console/console.h> #include <device/device.h> #include <soc/addressmap.h> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2abeb3a..09537a1 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -4,7 +4,6 @@ #include <device/pci_ops.h> #include <arch/symbols.h> #include <assert.h> -#include <bootmode.h> #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 54d6134..3b7aa40 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -2,7 +2,6 @@
#include <stdint.h> #include <arch/romstage.h> -#include <bootmode.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index b14bb72..a1ef06e 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <bootmode.h> #include <bootstate.h> #include <cbmem.h> #include <fsp/api.h>
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41670 )
Change subject: src: Remove unused 'include <bootmode.h>' ......................................................................
Patch Set 5:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4588 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4587 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4586 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4585
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
-
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)