Patch set updated for coreboot: southbridge/amd/sb700: Add option to disable SATA ALPM

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11993

-gerrit

commit 4e6e8df6134e903737f3c0a8c6efb85ec85b619f
Author: Timothy Pearson 
Date:   Thu Jun 18 11:48:02 2015 -0500

southbridge/amd/sb700: Add option to disable SATA ALPM

The AMD Register Programming Reference states that the user should
    have the option to disable Active Link Power Management for two
    reasons.  First, some drives may not function correctly with the
    ALPM implementation of the SP5100, and second there are some
    situations where low latency access is more important than the
    power savings created by using ALPM.

Allow the user to disable ALPM if desired.

Change-Id: I88055cbb4df4d7ba811cef7056c0a6ca2612fcb0
    Signed-off-by: Timothy Pearson 
---
 src/southbridge/amd/sb700/sata.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index fdf32c7..c61fa01 100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -104,6 +104,7 @@ static void sata_init(struct device *dev)
    int i, j;
    uint8_t nvram;
    uint8_t sata_ahci_mode;
+	uint8_t sata_alpm_enable;
    uint8_t port_count;
    uint8_t max_port_count;

@@ -111,6 +112,10 @@ static void sata_init(struct device *dev)
    if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS)
    	sata_ahci_mode = !!nvram;

+	sata_alpm_enable = 0;
+	if (get_option(&nvram, "sata_alpm") == CB_SUCCESS)
+		sata_alpm_enable = !!nvram;
+
    device_t sm_dev;
    /* SATA SMBus Disable */
    sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -229,6 +234,13 @@ static void sata_init(struct device *dev)
    	dword &= ~(0x1 << i);
    write32(sata_bar5 + 0x0c, dword);

+	/* Disable ALPM if ALPM support not requested */
+	if (!sata_alpm_enable) {
+		dword = read32(sata_bar5 + 0xfc);
+		dword &= ~(0x1 << 11);	/* Disable ALPM */
+		write32(sata_bar5 + 0xfc, dword);
+	}
+
    /* Write protect Sub-Class Code */
    byte = pci_read_config8(dev, 0x40);
    byte &= ~(1 << 0);