[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74839 )

Change subject: soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range
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soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range

Since the 16MByte of memory-mapped SPI flash region right below the 4GB
boundary is both a fixed region and isn't decoded on a device below the
LPC device, but assumed to be decoded by the LPC device itself, it
shouldn't be reported as a subtractive resource, but as an MMIO resource
instead.

TEST=On mandolin the 16MByte MMIO-mapped SPI flash now show up as a
reserved region in the e820 memory map which wasn't the case before:

13. 00000000ff000000-00000000ffffffff: RESERVED

The Linux kernel doesn't show any new or possibly related errors.

Signed-off-by: Felix Held 
Suggested-by: Kyösti Mälkki 
Change-Id: Ib52df2b2d79a1e6213c3499984a5a1e0e25c058a
---
M src/soc/amd/common/block/lpc/lpc.c
1 file changed, 26 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/74839/1

diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 1fbff53..b8fb923 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -117,11 +117,8 @@
    	     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

/* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->base = FLASH_BELOW_4GB_MAPPING_REGION_BASE;
-	res->size = FLASH_BELOW_4GB_MAPPING_REGION_SIZE;
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	mmio_range(dev, 1, FLASH_BELOW_4GB_MAPPING_REGION_BASE,
+		   FLASH_BELOW_4GB_MAPPING_REGION_SIZE);

/* Add a memory resource for the SPI BAR. */
    mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB);