New patch to review for coreboot: bd05142 AMD Kabini: change memory layout

[WANG Siyuan]

WANG Siyuan ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5358

-gerrit

commit bd051426a9e5a3a4766c8509f6cf7c8cbe63efab
Author: WANG Siyuan 
Date:   Mon Mar 10 15:39:57 2014 +0800

AMD Kabini: change memory layout

According to BKDG, from TOM to 4G is MMIO space. In the current setting,
    TOM is 0xE0000000 and MMCONF_BASE_ADDRESS is 0xA0000000. This is not
    correct.Take 4G memory as an example, the current memory layout is:
      0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
      1. 0000000000001000-000000000009ffff: RAM
      2. 00000000000c0000-000000009fffffff: RAM
      3. 00000000a0000000-00000000afffffff: RESERVED (PCIe configration space)
      4. 00000000b0000000-00000000bf13efff: RAM
      5. 00000000bf13f000-00000000bfffffff: CONFIGURATION TABLES
      6. 00000000c0000000-00000000dfffffff: RESERVED (UMA memory)
      7. 0000000100000000-000000011fffffff: RAM

In this patch, change TOM to 0xC0000000 and change MMCONF_BASE_ADDRESS
    to 0xC0000000. Take 4G memory as an example, the new memory layout is:
      0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
      1. 0000000000001000-000000000009ffff: RAM
      2. 00000000000c0000-000000009f12ffff: RAM
      3. 000000009f130000-000000009fffffff: CONFIGURATION TABLES
      4. 00000000a0000000-00000000cfffffff: RESERVED (UMA memory and PCIe configration space)
      5. 0000000100000000-000000013fffffff: RAM

I have tested on OliveHill with 2G, 4G and 8G memory. coreboot+seabios
    can boot to Windows 7 and Ubuntu 13.10. S3 is good in both of them.

Change-Id: Icdb36bca384c34e9c2c6798162b36c07df0149f8
    Signed-off-by: WANG Siyuan 
    Signed-off-by: WANG Siyuan 
---
 src/mainboard/amd/olivehill/agesawrapper.c   | 1 +
 src/mainboard/asrock/imb-a180/agesawrapper.c | 1 +
 src/northbridge/amd/agesa/family16kb/Kconfig | 2 +-
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c
index a1cf7de..00997fb 100644
--- a/src/mainboard/amd/olivehill/agesawrapper.c
+++ b/src/mainboard/amd/olivehill/agesawrapper.c
@@ -291,6 +291,7 @@ agesawrapper_amdinitpost (

AmdCreateStruct (&AmdParamStruct);
    PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
+	PostParams->MemConfig.BottomIo = 0xC0;
    status = AmdInitPost (PostParams);
    if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
    AmdReleaseStruct (&AmdParamStruct);
diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c
index 0f9212f..c64cfe1 100644
--- a/src/mainboard/asrock/imb-a180/agesawrapper.c
+++ b/src/mainboard/asrock/imb-a180/agesawrapper.c
@@ -291,6 +291,7 @@ agesawrapper_amdinitpost (

AmdCreateStruct (&AmdParamStruct);
    PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
+	PostParams->MemConfig.BottomIo = 0xC0;
    status = AmdInitPost (PostParams);
    if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
    AmdReleaseStruct (&AmdParamStruct);
diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig
index 259195b..db186f9 100644
--- a/src/northbridge/amd/agesa/family16kb/Kconfig
+++ b/src/northbridge/amd/agesa/family16kb/Kconfig
@@ -32,7 +32,7 @@ config HW_MEM_HOLE_SIZE_AUTO_INC

config MMCONF_BASE_ADDRESS
    hex
-	default 0xA0000000
+	default 0xC0000000

config MMCONF_BUS_NUMBER
    int