Change in coreboot[master]: 3rdparty/blobs: Commit updated blobs

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25183

Change subject: 3rdparty/blobs: Commit updated blobs
......................................................................

3rdparty/blobs: Commit updated blobs

AGESA.bin was merged to blobs/pi/amd/00670F00/FT4. Commit the updated blobs
and update AGESA.h to match AGESA.bin.

BUG=b:70338633
TEST=build kahlee.

Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566
Signed-off-by: Richard Spiegel 
---
M 3rdparty/blobs
M src/vendorcode/amd/pi/00670F00/AGESA.h
2 files changed, 20 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/25183/1

diff --git a/3rdparty/blobs b/3rdparty/blobs
index 19dea8d..a4b5613 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit 19dea8d171544f01f12ee6b78af0cc356ab994aa
+Subproject commit a4b561391f59e09059ce851fa19b64ca945672d5
diff --git a/src/vendorcode/amd/pi/00670F00/AGESA.h b/src/vendorcode/amd/pi/00670F00/AGESA.h
index 17f6986..2b2a8b6 100644
--- a/src/vendorcode/amd/pi/00670F00/AGESA.h
+++ b/src/vendorcode/amd/pi/00670F00/AGESA.h
@@ -67,6 +67,7 @@
 #define AGESA_RUNFUNC_ON_ALL_APS                0x00028106ul
 #define AGESA_IDLE_AN_AP                        0x00028107ul
 #define AGESA_WAIT_FOR_ALL_APS                  0x00028108ul
+#define AGESA_HALT_THIS_AP                      0x00028109ul

// AGESA ADVANCED CALLOUTS, Memory
 #define AGESA_READ_SPD                 0x00028140ul
@@ -2514,6 +2515,18 @@
   IN OUT    MEM_DATA_STRUCT     *MemData;       ///< Location of the MemData structure, for reference
 } AGESA_READ_SPD_PARAMS;

+/// Parameters structure for the interface call-out AGESA_HALT_THIS_AP
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS StdHeader;   ///< Standard configuration header
+  IN        BOOLEAN           ExecWbinvd;  ///< Indicates whether to execute
+                                           ///  WBINVD
+  IN        BOOLEAN           PrimaryCore; ///< Indicates whether current core
+                                           ///  is the primary core of the
+                                           ///  compute unit
+  IN        BOOLEAN           CacheEn;     ///< Indicates whether cache should
+                                           ///  be enabled
+} AGESA_HALT_THIS_AP_PARAMS;
+
 /// VoltageType values
 typedef enum {
   VTYPE_CPU_VREF,                                    ///< Cpu side Vref
@@ -2625,6 +2638,12 @@
   );

AGESA_STATUS
+AgesaHaltThisAp (
+  IN       UINTN                      FcnData,
+  IN       AGESA_HALT_THIS_AP_PARAMS  *HaltApParams
+);
+
+AGESA_STATUS
 AgesaHookBeforeDramInit (
   IN        UINTN               SocketIdModuleId,
   IN OUT    MEM_DATA_STRUCT     *MemData