Attention is currently required from: Michał Kopeć, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63578 )
Change subject: [HACK] Add an option to use ADL-S IOT FSP ......................................................................
Patch Set 11: Verified-1
(183 comments)
File src/soc/intel/alderlake/include/fsp/FirmwareVersionInfoHob.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/21ff5bc3_e1d6a42a PS11, Line 29: UINT8 MajorVersion; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/18fbe2e2_fcdf1644 PS11, Line 30: UINT8 MinorVersion; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/05f2399f_dd1332d3 PS11, Line 31: UINT8 Revision; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/33e80b8e_56898365 PS11, Line 32: UINT16 BuildNumber; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/660183a4_940713a2 PS11, Line 39: UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/cb76dd41_b3d6e410 PS11, Line 39: UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/ddfa3a9e_46f315d3 PS11, Line 40: UINT8 VersionStringIndex; ///< Offset 1 Index of Version String line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/c85b8fd2_d5bbbacd PS11, Line 40: UINT8 VersionStringIndex; ///< Offset 1 Index of Version String please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/7be299a4_28f0d4a1 PS11, Line 41: FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/34e2cbdd_29d8482a PS11, Line 49: UINT8 Type; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/73919722_e3fad57c PS11, Line 50: UINT8 Length; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/490ee3f3_5dbb9174 PS11, Line 51: UINT16 Handle; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/f5e6da46_68091651 PS11, Line 59: EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/244e7835_d9207c95 PS11, Line 59: EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/436249db_db9d35e1 PS11, Line 60: SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/dc314b15_06a26a06 PS11, Line 60: SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/464dfb16_bee63d8a PS11, Line 61: UINT8 Count; ///< Offset 28 Number of FVI elements included. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/66a17acf_4e015e84 PS11, Line 61: UINT8 Count; ///< Offset 28 Number of FVI elements included. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/2d778c52_ad1f1eb0 PS11, Line 68: #endif // _FIRMWARE_VERSION_INFO_HOB_H_ adding a line without newline at end of file
File src/soc/intel/alderlake/include/fsp/MemInfoHob.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/cdc8fed9_30c8f6ad PS11, Line 22: #pragma pack (push, 1) space prohibited between function name and open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/2e2ec178_5b82e8fc PS11, Line 50: UINT16 HobType; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/9f9f389e_34c80af2 PS11, Line 51: UINT16 HobLength; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/d7857b86_506ba8bd PS11, Line 52: UINT32 Reserved; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/4a43e796_404d4511 PS11, Line 56: EFI_HOB_GENERIC_HEADER Header; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/f6f97cab_c04d5bad PS11, Line 57: EFI_GUID Name; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/b77ad667_bb6ccd3a PS11, Line 80: UINT8 Major; ///< Major version number please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/76387b9d_e2efcd9d PS11, Line 81: UINT8 Minor; ///< Minor version number please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/86eac29d_dbac6fcb PS11, Line 82: UINT8 Rev; ///< Revision number please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/78c2ba9a_379b9c91 PS11, Line 83: UINT8 Build; ///< Build number please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/357e80af_0b4a6b5c PS11, Line 109: #define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/5819ab14_d06b0438 PS11, Line 119: #define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/28975806_ce2c6173 PS11, Line 124: bmCold, ///< Cold boot please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/d25910ba_57e7b7de PS11, Line 125: bmWarm, ///< Warm boot please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/d6b0f3be_d089ef4e PS11, Line 126: bmS3, ///< S3 resume please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/719268b7_b0c797b0 PS11, Line 127: bmFast, ///< Fast boot please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/33fc2c0d_d2fca11d PS11, Line 128: MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/295aeb75_27c503c7 PS11, Line 129: MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/3fad50c8_8d23fc10 PS11, Line 129: MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/1eaba242_4b90b395 PS11, Line 159: UINT32 tCK; ///< Memory cycle time, in femtoseconds. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/62348c80_fbdb017c PS11, Line 160: UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/dc8227cb_8f5071ac PS11, Line 161: UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/097c975f_4a59a241 PS11, Line 162: UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/15e92000_e194ec09 PS11, Line 162: UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/ba9be20e_163a212b PS11, Line 163: UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/8c04a8c4_9d821603 PS11, Line 163: UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/33c33fba_beec728c PS11, Line 164: UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/8f5d60e5_f52397c3 PS11, Line 164: UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/0412812b_92a6b0f4 PS11, Line 165: UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/983213b5_e650a046 PS11, Line 165: UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/e04265f7_8ebeac39 PS11, Line 166: UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/87104cdd_26127325 PS11, Line 166: UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/1db7665f_e266130e PS11, Line 167: UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/d8048d43_373b9913 PS11, Line 167: UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/ab94c263_1cfcdfa5 PS11, Line 168: UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/57bd6114_220147cd PS11, Line 168: UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/81aac84e_39d5eff9 PS11, Line 169: UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/568ddc80_138cbcc7 PS11, Line 169: UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/1a5dcd60_ee8590fe PS11, Line 170: UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/050cd025_bb4b6c23 PS11, Line 170: UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/56834c94_8640ab34 PS11, Line 171: UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/9533e204_63535f7c PS11, Line 171: UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/c868f6fd_a6068e22 PS11, Line 172: UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/a5c287a2_9eeb18c6 PS11, Line 172: UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/a9d3bffc_3598edc4 PS11, Line 173: UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/a0a9594b_23caee76 PS11, Line 173: UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/eebc7241_1556784e PS11, Line 174: UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/6d8e7c84_b6fa0fb8 PS11, Line 174: UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/36fb8d03_f42879e3 PS11, Line 175: UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/5120846c_2497179a PS11, Line 175: UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/6528e505_fbe4d777 PS11, Line 176: UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/6baa6f47_27b672f6 PS11, Line 176: UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/c7f9ee07_182dad3c PS11, Line 177: UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/8ee39176_e72f29c6 PS11, Line 177: UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/29e64584_79adf6f1 PS11, Line 178: UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/dbab9b8a_dedd3f97 PS11, Line 178: UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/37307166_af84e7e1 PS11, Line 179: UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/e740d052_247442c3 PS11, Line 179: UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/07937d3c_270c2a49 PS11, Line 180: UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/d85354a1_842a70ad PS11, Line 180: UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/58e0041b_20d01f85 PS11, Line 184: UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/72fe1b95_891aeddd PS11, Line 191: UINT8 Status; ///< See MrcDimmStatus for the definition of this field. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/05d2960a_37fba7ff PS11, Line 191: UINT8 Status; ///< See MrcDimmStatus for the definition of this field. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/ffdd4724_ee6f2709 PS11, Line 192: UINT8 DimmId; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/fd7bc52e_a17a4689 PS11, Line 193: UINT32 DimmCapacity; ///< DIMM size in MBytes. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/485d734d_95efa344 PS11, Line 194: UINT16 MfgId; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/af174fd8_705d7d24 PS11, Line 195: UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/847063c3_5c292f9f PS11, Line 195: UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/9b11a0f7_e3169b73 PS11, Line 196: UINT8 RankInDimm; ///< The number of ranks in this DIMM. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/45e787f8_80fa1bef PS11, Line 197: UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/c8e9b720_6cb6241c PS11, Line 197: UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/95eff266_72859b0d PS11, Line 198: UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/ca42da84_8467f962 PS11, Line 198: UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/2e7c9a96_71c26b32 PS11, Line 199: UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/fa9e7cd1_00ba86e3 PS11, Line 199: UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/f0141bd9_059b121f PS11, Line 200: UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/09a1b97d_6e66bf0d PS11, Line 200: UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/9e156350_5a0b0a0e PS11, Line 201: UINT16 Speed; ///< The maximum capable speed of the device, in MHz please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/298d328f_1c438440 PS11, Line 202: UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/687d1205_5a9b2be1 PS11, Line 202: UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/08ea5bbb_1a2eb3bf PS11, Line 206: UINT8 Status; ///< Indicates whether this channel should be used. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/9fbfdeb0_2af7ae59 PS11, Line 207: UINT8 ChannelId; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/582a0ef5_052ca2ef PS11, Line 208: UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/444b081c_d2d05ff2 PS11, Line 208: UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/1b01146d_6480deb0 PS11, Line 209: MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/a3135e62_37510729 PS11, Line 210: DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/005feb81_6dd92146 PS11, Line 214: UINT8 Status; ///< Indicates whether this controller should be used. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/cbe25f71_6c67066a PS11, Line 214: UINT8 Status; ///< Indicates whether this controller should be used. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/be9c0c1e_d21eef76 PS11, Line 215: UINT16 DeviceId; ///< The PCI device id of this memory controller. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/7808ae85_334ee403 PS11, Line 216: UINT8 RevisionId; ///< The PCI revision id of this memory controller. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/cf2941e0_42b50088 PS11, Line 217: UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/85998cd1_0c830451 PS11, Line 217: UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/ac22cfde_6f2cf199 PS11, Line 218: CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/f77ec720_46751b2f PS11, Line 222: UINT64 BaseAddress; ///< Trace Base Address please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/fb6c3ef8_14d8ba49 PS11, Line 223: UINT64 TotalSize; ///< Total Trace Region of Same Cache type please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/c6886a8f_eff07032 PS11, Line 224: UINT8 CacheType; ///< Trace Cache Type please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/5bd3dcd5_a06a5d9f PS11, Line 225: UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/08b721c2_68cc3e5b PS11, Line 226: UINT8 Rsvd[2]; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/463a582d_40477f65 PS11, Line 231: UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/2bae7fd7_d35b4289 PS11, Line 232: MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/2f76b69a_250912b3 PS11, Line 232: MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/9a85e472_c700bf8d PS11, Line 233: MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/5dd6597d_ce99dd7a PS11, Line 233: MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/2232e94f_35e45d17 PS11, Line 238: UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/de0fb1cd_c22c6cc0 PS11, Line 238: UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/1cf0a4e7_3ca88d16 PS11, Line 239: UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/8a393c88_c43e7c10 PS11, Line 239: UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/92c2dff5_a3667123 PS11, Line 240: HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/d34eae01_bedc3267 PS11, Line 244: UINT8 Revision; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/e2762d57_4f5e1f3d PS11, Line 245: UINT16 DataWidth; ///< Data width, in bits, of this memory device please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/dd73ab58_71647b6b PS11, Line 249: UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/fbca6b93_650704f3 PS11, Line 250: UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/a040dae8_5403f179 PS11, Line 250: UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/cb5e9c25_ab5aac72 PS11, Line 251: UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/7cec4e86_7739216f PS11, Line 251: UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/0c6db4c5_2d789884 PS11, Line 255: UINT8 ErrorCorrectionType; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/96ae8481_60a4abbf PS11, Line 257: SiMrcVersion Version; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/08d5a774_5bf9aa5b PS11, Line 258: BOOLEAN EccSupport; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/37a9453c_96e98ef7 PS11, Line 259: UINT8 MemoryProfile; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/8b0d61b7_7dab8183 PS11, Line 260: UINT8 IsDMBRunning; ///< Deprecated. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/8a6d5f2b_0de6762a PS11, Line 261: UINT32 TotalPhysicalMemorySize; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/98f4dfc6_41bd8cb7 PS11, Line 262: UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/012ef28d_c40bd886 PS11, Line 262: UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/8ddae3e5_295dba83 PS11, Line 264: /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/3d6ea6e8_25384194 PS11, Line 271: UINT8 XmpProfileEnable; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/1b51222c_dd87c671 PS11, Line 272: UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/217f69bb_47a979cf PS11, Line 272: UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/c1df5492_3a0a0fb8 PS11, Line 273: UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/c274003f_ee349546 PS11, Line 274: UINT8 RefClk; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/e06a15bc_66fb3819 PS11, Line 275: UINT32 VddVoltage[MAX_PROFILE_NUM]; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/0a6fc054_fafbdf4d PS11, Line 276: UINT32 VddqVoltage[MAX_PROFILE_NUM]; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/d2f8aa1e_d8a4bd24 PS11, Line 277: UINT32 VppVoltage[MAX_PROFILE_NUM]; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/ca81cb06_d8c91413 PS11, Line 278: CONTROLLER_INFO Controller[MAX_NODE]; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/ccd0bd15_391fd277 PS11, Line 279: UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/5f6ef3b3_0cb953ea PS11, Line 279: UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/f94a81c0_fc923c54 PS11, Line 280: UINT32 NumPopulatedChannels; ///< Total number of memory channels populated line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/519e600a_388072a8 PS11, Line 280: UINT32 NumPopulatedChannels; ///< Total number of memory channels populated please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/edc78962_0cdf1487 PS11, Line 281: HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/1fb1af91_bb7c2bf4 PS11, Line 281: HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/c6452df2_8268aace PS11, Line 282: UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/bb03f522_2c848955 PS11, Line 282: UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/f078bb5f_79ae4fe0 PS11, Line 283: BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/72b14cc3_23242370 PS11, Line 283: BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/969ce4b8_88adb44a PS11, Line 284: BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/af3335a4_429a57e2 PS11, Line 284: BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/31be57bd_732c51ed PS11, Line 285: BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/d3864850_965718a2 PS11, Line 285: BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/4dd1ea39_2e1ddade PS11, Line 297: UINT8 Revision; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/5670e50c_e4c978c8 PS11, Line 298: UINT8 Reserved[3]; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/1259a78e_196c0588 PS11, Line 299: UINT32 BootMode; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/951a9264_071ce70b PS11, Line 300: UINT32 TsegSize; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/9f332b5c_acf69275 PS11, Line 301: UINT32 TsegBase; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/68cf7255_103fb022 PS11, Line 302: UINT32 PrmrrSize; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/ce689937_395b6779 PS11, Line 303: UINT64 PrmrrBase; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/7502f648_e02c3588 PS11, Line 304: UINT32 GttBase; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/1fa70ebc_ac4542a3 PS11, Line 305: UINT32 MmioSize; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/59ece31b_1ac40a88 PS11, Line 306: UINT32 PciEBaseAddress; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/443e279c_98963add PS11, Line 307: PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/e86eca1f_d8eaa295 PS11, Line 308: PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/41e6465c_da1695a3 PS11, Line 309: BOOLEAN MrcBasicMemoryTestPass; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/0b812e01_6b3efb4a PS11, Line 313: EFI_HOB_GUID_TYPE EfiHobGuidType; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/17ee660a_fa2bf7a4 PS11, Line 314: MEMORY_PLATFORM_DATA Data; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/32bee620_f145d7be PS11, Line 315: UINT8 *Buffer; please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150366): https://review.coreboot.org/c/coreboot/+/63578/comment/7574da93_21186671 PS11, Line 318: #pragma pack (pop) space prohibited between function name and open parenthesis '('