Change in coreboot[master]: superio/aspeed/ast2400: Fix Register Offset

[Christian Walter (Code Review)]

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38565 )

Change subject: superio/aspeed/ast2400: Fix Register Offset
......................................................................

superio/aspeed/ast2400: Fix Register Offset

According to the specification the register offset must be 0x71 instead
of 0x70.

Change-Id: Icf69ffc701a42a31a4545ce53c13e2c2554863e1
Signed-off-by: Christian Walter 
---
M src/superio/aspeed/ast2400/superio.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38565/1

diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c
index 37a7c9d..6f2cbcd 100644
--- a/src/superio/aspeed/ast2400/superio.c
+++ b/src/superio/aspeed/ast2400/superio.c
@@ -35,7 +35,7 @@
    	pnp_enter_conf_mode(dev);
    	pnp_set_logical_device(dev);
    	/* In ESPI mode must write 0 to IRQ level on every LDN */
-		pnp_write_config(dev, 0x70, 0);
+		pnp_write_config(dev, 0x71, 0);
    	pnp_exit_conf_mode(dev);
    }

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38565 )

Change subject: superio/aspeed/ast2400: Fix Register Offset
......................................................................

Patch Set 1: Code-Review+2

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38565 )

Change subject: superio/aspeed/ast2400: Fix Register Offset
......................................................................

Patch Set 1: Code-Review+2

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38565 )

Change subject: superio/aspeed/ast2400: Fix Register Offset
......................................................................

superio/aspeed/ast2400: Fix Register Offset

According to the specification the register offset must be 0x71 instead
of 0x70.

Change-Id: Icf69ffc701a42a31a4545ce53c13e2c2554863e1
Signed-off-by: Christian Walter 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38565
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
Reviewed-by: Felix Held 
---
M src/superio/aspeed/ast2400/superio.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c
index 37a7c9d..6f2cbcd 100644
--- a/src/superio/aspeed/ast2400/superio.c
+++ b/src/superio/aspeed/ast2400/superio.c
@@ -35,7 +35,7 @@
    	pnp_enter_conf_mode(dev);
    	pnp_set_logical_device(dev);
    	/* In ESPI mode must write 0 to IRQ level on every LDN */
-		pnp_write_config(dev, 0x70, 0);
+		pnp_write_config(dev, 0x71, 0);
    	pnp_exit_conf_mode(dev);
    }

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38565 )

Change subject: superio/aspeed/ast2400: Fix Register Offset
......................................................................

Patch Set 2:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/295
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/294
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/293

Please note: This test is under development and might not be accurate at all!